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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81850 91177308-0d34-0410-b5e6-96231b3b80d8
577 lines
24 KiB
C++
577 lines
24 KiB
C++
//===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass. Given some numbering of
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// each the machine instructions (in this implemention depth-first order) an
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// interval [i, j) is said to be a live interval for register v if there is no
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// instruction with number j' > j such that v is live at j' and there is no
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// instruction with number i' < i such that v is live at i'. In this
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// implementation intervals can have holes, i.e. an interval might look like
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// [1,20), [50,65), [1000,1001).
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/Allocator.h"
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#include <cmath>
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namespace llvm {
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class AliasAnalysis;
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class LiveVariables;
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class MachineLoopInfo;
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class TargetRegisterInfo;
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class MachineRegisterInfo;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class VirtRegMap;
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typedef std::pair<MachineInstrIndex, MachineBasicBlock*> IdxMBBPair;
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inline bool operator<(MachineInstrIndex V, const IdxMBBPair &IM) {
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return V < IM.first;
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}
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inline bool operator<(const IdxMBBPair &IM, MachineInstrIndex V) {
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return IM.first < V;
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}
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struct Idx2MBBCompare {
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bool operator()(const IdxMBBPair &LHS, const IdxMBBPair &RHS) const {
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return LHS.first < RHS.first;
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}
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};
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class LiveIntervals : public MachineFunctionPass {
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MachineFunction* mf_;
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MachineRegisterInfo* mri_;
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const TargetMachine* tm_;
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const TargetRegisterInfo* tri_;
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const TargetInstrInfo* tii_;
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AliasAnalysis *aa_;
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LiveVariables* lv_;
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/// Special pool allocator for VNInfo's (LiveInterval val#).
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///
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BumpPtrAllocator VNInfoAllocator;
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/// MBB2IdxMap - The indexes of the first and last instructions in the
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/// specified basic block.
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std::vector<std::pair<MachineInstrIndex, MachineInstrIndex> > MBB2IdxMap;
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/// Idx2MBBMap - Sorted list of pairs of index of first instruction
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/// and MBB id.
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std::vector<IdxMBBPair> Idx2MBBMap;
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/// FunctionSize - The number of instructions present in the function
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uint64_t FunctionSize;
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typedef DenseMap<const MachineInstr*, MachineInstrIndex> Mi2IndexMap;
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Mi2IndexMap mi2iMap_;
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typedef std::vector<MachineInstr*> Index2MiMap;
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Index2MiMap i2miMap_;
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typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
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Reg2IntervalMap r2iMap_;
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DenseMap<MachineBasicBlock*, MachineInstrIndex> terminatorGaps;
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/// phiJoinCopies - Copy instructions which are PHI joins.
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SmallVector<MachineInstr*, 16> phiJoinCopies;
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/// allocatableRegs_ - A bit vector of allocatable registers.
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BitVector allocatableRegs_;
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/// CloneMIs - A list of clones as result of re-materialization.
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std::vector<MachineInstr*> CloneMIs;
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typedef LiveInterval::InstrSlots InstrSlots;
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public:
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static char ID; // Pass identification, replacement for typeid
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LiveIntervals() : MachineFunctionPass(&ID) {}
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MachineInstrIndex getBaseIndex(MachineInstrIndex index) {
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return MachineInstrIndex(index, MachineInstrIndex::LOAD);
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}
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MachineInstrIndex getBoundaryIndex(MachineInstrIndex index) {
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return MachineInstrIndex(index,
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(MachineInstrIndex::Slot)(MachineInstrIndex::NUM - 1));
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}
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MachineInstrIndex getLoadIndex(MachineInstrIndex index) {
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return MachineInstrIndex(index, MachineInstrIndex::LOAD);
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}
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MachineInstrIndex getUseIndex(MachineInstrIndex index) {
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return MachineInstrIndex(index, MachineInstrIndex::USE);
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}
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MachineInstrIndex getDefIndex(MachineInstrIndex index) {
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return MachineInstrIndex(index, MachineInstrIndex::DEF);
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}
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MachineInstrIndex getStoreIndex(MachineInstrIndex index) {
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return MachineInstrIndex(index, MachineInstrIndex::STORE);
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}
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MachineInstrIndex getNextSlot(MachineInstrIndex m) const {
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return m.nextSlot_();
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}
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MachineInstrIndex getNextIndex(MachineInstrIndex m) const {
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return m.nextIndex_();
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}
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MachineInstrIndex getPrevSlot(MachineInstrIndex m) const {
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return m.prevSlot_();
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}
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MachineInstrIndex getPrevIndex(MachineInstrIndex m) const {
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return m.prevIndex_();
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}
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static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
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return (isDef + isUse) * powf(10.0F, (float)loopDepth);
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}
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typedef Reg2IntervalMap::iterator iterator;
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typedef Reg2IntervalMap::const_iterator const_iterator;
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const_iterator begin() const { return r2iMap_.begin(); }
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const_iterator end() const { return r2iMap_.end(); }
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iterator begin() { return r2iMap_.begin(); }
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iterator end() { return r2iMap_.end(); }
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unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
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LiveInterval &getInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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assert(I != r2iMap_.end() && "Interval does not exist for register");
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return *I->second;
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}
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const LiveInterval &getInterval(unsigned reg) const {
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Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
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assert(I != r2iMap_.end() && "Interval does not exist for register");
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return *I->second;
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}
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bool hasInterval(unsigned reg) const {
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return r2iMap_.count(reg);
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}
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/// getMBBStartIdx - Return the base index of the first instruction in the
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/// specified MachineBasicBlock.
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MachineInstrIndex getMBBStartIdx(MachineBasicBlock *MBB) const {
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return getMBBStartIdx(MBB->getNumber());
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}
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MachineInstrIndex getMBBStartIdx(unsigned MBBNo) const {
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assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
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return MBB2IdxMap[MBBNo].first;
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}
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/// getMBBEndIdx - Return the store index of the last instruction in the
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/// specified MachineBasicBlock.
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MachineInstrIndex getMBBEndIdx(MachineBasicBlock *MBB) const {
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return getMBBEndIdx(MBB->getNumber());
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}
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MachineInstrIndex getMBBEndIdx(unsigned MBBNo) const {
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assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
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return MBB2IdxMap[MBBNo].second;
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}
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/// getScaledIntervalSize - get the size of an interval in "units,"
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/// where every function is composed of one thousand units. This
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/// measure scales properly with empty index slots in the function.
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double getScaledIntervalSize(LiveInterval& I) {
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return (1000.0 / InstrSlots::NUM * I.getSize()) / i2miMap_.size();
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}
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/// getApproximateInstructionCount - computes an estimate of the number
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/// of instructions in a given LiveInterval.
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unsigned getApproximateInstructionCount(LiveInterval& I) {
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double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
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return (unsigned)(IntervalPercentage * FunctionSize);
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}
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/// getMBBFromIndex - given an index in any instruction of an
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/// MBB return a pointer the MBB
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MachineBasicBlock* getMBBFromIndex(MachineInstrIndex index) const {
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std::vector<IdxMBBPair>::const_iterator I =
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std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), index);
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// Take the pair containing the index
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std::vector<IdxMBBPair>::const_iterator J =
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((I != Idx2MBBMap.end() && I->first > index) ||
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(I == Idx2MBBMap.end() && Idx2MBBMap.size()>0)) ? (I-1): I;
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assert(J != Idx2MBBMap.end() && J->first <= index &&
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index <= getMBBEndIdx(J->second) &&
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"index does not correspond to an MBB");
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return J->second;
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}
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/// getInstructionIndex - returns the base index of instr
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MachineInstrIndex getInstructionIndex(const MachineInstr* instr) const {
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Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
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assert(it != mi2iMap_.end() && "Invalid instruction!");
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return it->second;
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}
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/// getInstructionFromIndex - given an index in any slot of an
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/// instruction return a pointer the instruction
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MachineInstr* getInstructionFromIndex(MachineInstrIndex index) const {
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// convert index to vector index
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unsigned i = index.getVecIndex();
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assert(i < i2miMap_.size() &&
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"index does not correspond to an instruction");
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return i2miMap_[i];
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}
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/// hasGapBeforeInstr - Return true if the previous instruction slot,
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/// i.e. Index - InstrSlots::NUM, is not occupied.
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bool hasGapBeforeInstr(MachineInstrIndex Index) {
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Index = getBaseIndex(getPrevIndex(Index));
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return getInstructionFromIndex(Index) == 0;
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}
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/// hasGapAfterInstr - Return true if the successive instruction slot,
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/// i.e. Index + InstrSlots::Num, is not occupied.
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bool hasGapAfterInstr(MachineInstrIndex Index) {
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Index = getBaseIndex(getNextIndex(Index));
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return getInstructionFromIndex(Index) == 0;
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}
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/// findGapBeforeInstr - Find an empty instruction slot before the
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/// specified index. If "Furthest" is true, find one that's furthest
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/// away from the index (but before any index that's occupied).
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MachineInstrIndex findGapBeforeInstr(MachineInstrIndex Index,
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bool Furthest = false) {
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Index = getBaseIndex(getPrevIndex(Index));
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if (getInstructionFromIndex(Index))
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return MachineInstrIndex(); // No gap!
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if (!Furthest)
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return Index;
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MachineInstrIndex PrevIndex = getBaseIndex(getPrevIndex(Index));
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while (getInstructionFromIndex(Index)) {
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Index = PrevIndex;
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PrevIndex = getBaseIndex(getPrevIndex(Index));
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}
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return Index;
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}
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/// InsertMachineInstrInMaps - Insert the specified machine instruction
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/// into the instruction index map at the given index.
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void InsertMachineInstrInMaps(MachineInstr *MI, MachineInstrIndex Index) {
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i2miMap_[Index.getVecIndex()] = MI;
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Mi2IndexMap::iterator it = mi2iMap_.find(MI);
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assert(it == mi2iMap_.end() && "Already in map!");
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mi2iMap_[MI] = Index;
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}
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/// conflictsWithPhysRegDef - Returns true if the specified register
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/// is defined during the duration of the specified interval.
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bool conflictsWithPhysRegDef(const LiveInterval &li, VirtRegMap &vrm,
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unsigned reg);
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/// conflictsWithPhysRegRef - Similar to conflictsWithPhysRegRef except
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/// it can check use as well.
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bool conflictsWithPhysRegRef(LiveInterval &li, unsigned Reg,
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bool CheckUse,
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SmallPtrSet<MachineInstr*,32> &JoinedCopies);
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/// findLiveInMBBs - Given a live range, if the value of the range
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/// is live in any MBB returns true as well as the list of basic blocks
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/// in which the value is live.
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bool findLiveInMBBs(MachineInstrIndex Start, MachineInstrIndex End,
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SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
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/// findReachableMBBs - Return a list MBB that can be reached via any
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/// branch or fallthroughs. Return true if the list is not empty.
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bool findReachableMBBs(MachineInstrIndex Start, MachineInstrIndex End,
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SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
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// Interval creation
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LiveInterval &getOrCreateInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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if (I == r2iMap_.end())
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I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
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return *I->second;
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}
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/// dupInterval - Duplicate a live interval. The caller is responsible for
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/// managing the allocated memory.
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LiveInterval *dupInterval(LiveInterval *li);
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/// addLiveRangeToEndOfBlock - Given a register and an instruction,
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/// adds a live range from that instruction to the end of its MBB.
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LiveRange addLiveRangeToEndOfBlock(unsigned reg,
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MachineInstr* startInst);
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// Interval removal
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void removeInterval(unsigned Reg) {
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DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
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delete I->second;
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r2iMap_.erase(I);
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}
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/// isNotInMIMap - returns true if the specified machine instr has been
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/// removed or was never entered in the map.
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bool isNotInMIMap(MachineInstr* instr) const {
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return !mi2iMap_.count(instr);
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}
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/// RemoveMachineInstrFromMaps - This marks the specified machine instr as
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/// deleted.
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void RemoveMachineInstrFromMaps(MachineInstr *MI) {
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// remove index -> MachineInstr and
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// MachineInstr -> index mappings
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Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
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if (mi2i != mi2iMap_.end()) {
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i2miMap_[mi2i->second.index/InstrSlots::NUM] = 0;
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mi2iMap_.erase(mi2i);
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}
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}
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/// ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in
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/// maps used by register allocator.
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void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
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Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
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if (mi2i == mi2iMap_.end())
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return;
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i2miMap_[mi2i->second.index/InstrSlots::NUM] = NewMI;
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Mi2IndexMap::iterator it = mi2iMap_.find(MI);
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assert(it != mi2iMap_.end() && "Invalid instruction!");
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MachineInstrIndex Index = it->second;
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mi2iMap_.erase(it);
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mi2iMap_[NewMI] = Index;
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}
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BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; }
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/// getVNInfoSourceReg - Helper function that parses the specified VNInfo
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/// copy field and returns the source register that defines it.
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unsigned getVNInfoSourceReg(const VNInfo *VNI) const;
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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/// print - Implement the dump method.
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virtual void print(raw_ostream &O, const Module* = 0) const;
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/// addIntervalsForSpills - Create new intervals for spilled defs / uses of
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/// the given interval. FIXME: It also returns the weight of the spill slot
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/// (if any is created) by reference. This is temporary.
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std::vector<LiveInterval*>
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addIntervalsForSpills(const LiveInterval& i,
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SmallVectorImpl<LiveInterval*> &SpillIs,
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const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
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/// addIntervalsForSpillsFast - Quickly create new intervals for spilled
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/// defs / uses without remat or splitting.
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std::vector<LiveInterval*>
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addIntervalsForSpillsFast(const LiveInterval &li,
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const MachineLoopInfo *loopInfo, VirtRegMap &vrm);
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/// spillPhysRegAroundRegDefsUses - Spill the specified physical register
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/// around all defs and uses of the specified interval. Return true if it
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/// was able to cut its interval.
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bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
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unsigned PhysReg, VirtRegMap &vrm);
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/// isReMaterializable - Returns true if every definition of MI of every
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/// val# of the specified interval is re-materializable. Also returns true
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/// by reference if all of the defs are load instructions.
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bool isReMaterializable(const LiveInterval &li,
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SmallVectorImpl<LiveInterval*> &SpillIs,
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bool &isLoad);
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/// isReMaterializable - Returns true if the definition MI of the specified
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/// val# of the specified interval is re-materializable.
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bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
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MachineInstr *MI);
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/// getRepresentativeReg - Find the largest super register of the specified
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/// physical register.
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unsigned getRepresentativeReg(unsigned Reg) const;
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/// getNumConflictsWithPhysReg - Return the number of uses and defs of the
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/// specified interval that conflicts with the specified physical register.
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unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
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unsigned PhysReg) const;
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/// processImplicitDefs - Process IMPLICIT_DEF instructions. Add isUndef
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/// marker to implicit_def defs and their uses.
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void processImplicitDefs();
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/// computeNumbering - Compute the index numbering.
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void computeNumbering();
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/// scaleNumbering - Rescale interval numbers to introduce gaps for new
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/// instructions
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void scaleNumbering(int factor);
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/// intervalIsInOneMBB - Returns true if the specified interval is entirely
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/// within a single basic block.
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bool intervalIsInOneMBB(const LiveInterval &li) const;
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private:
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/// computeIntervals - Compute live intervals.
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void computeIntervals();
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bool isProfitableToCoalesce(LiveInterval &DstInt, LiveInterval &SrcInt,
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SmallVector<MachineInstr*,16> &IdentCopies,
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SmallVector<MachineInstr*,16> &OtherCopies);
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void performEarlyCoalescing();
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/// handleRegisterDef - update intervals for a register def
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/// (calls handlePhysicalRegisterDef and
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/// handleVirtualRegisterDef)
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void handleRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI,
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MachineInstrIndex MIIdx,
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MachineOperand& MO, unsigned MOIdx);
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/// handleVirtualRegisterDef - update intervals for a virtual
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/// register def
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void handleVirtualRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI,
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MachineInstrIndex MIIdx, MachineOperand& MO,
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unsigned MOIdx,
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LiveInterval& interval);
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/// handlePhysicalRegisterDef - update intervals for a physical register
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/// def.
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void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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MachineInstrIndex MIIdx, MachineOperand& MO,
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LiveInterval &interval,
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MachineInstr *CopyMI);
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/// handleLiveInRegister - Create interval for a livein register.
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void handleLiveInRegister(MachineBasicBlock* mbb,
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MachineInstrIndex MIIdx,
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LiveInterval &interval, bool isAlias = false);
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/// getReMatImplicitUse - If the remat definition MI has one (for now, we
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/// only allow one) virtual register operand, then its uses are implicitly
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/// using the register. Returns the virtual register.
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unsigned getReMatImplicitUse(const LiveInterval &li,
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MachineInstr *MI) const;
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/// isValNoAvailableAt - Return true if the val# of the specified interval
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/// which reaches the given instruction also reaches the specified use
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/// index.
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bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
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MachineInstrIndex UseIdx) const;
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/// isReMaterializable - Returns true if the definition MI of the specified
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/// val# of the specified interval is re-materializable. Also returns true
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/// by reference if the def is a load.
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bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
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|
MachineInstr *MI,
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|
SmallVectorImpl<LiveInterval*> &SpillIs,
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|
bool &isLoad);
|
|
|
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/// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
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|
/// slot / to reg or any rematerialized load into ith operand of specified
|
|
/// MI. If it is successul, MI is updated with the newly created MI and
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|
/// returns true.
|
|
bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
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|
MachineInstr *DefMI, MachineInstrIndex InstrIdx,
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|
SmallVector<unsigned, 2> &Ops,
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|
bool isSS, int FrameIndex, unsigned Reg);
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|
|
|
/// canFoldMemoryOperand - Return true if the specified load / store
|
|
/// folding is possible.
|
|
bool canFoldMemoryOperand(MachineInstr *MI,
|
|
SmallVector<unsigned, 2> &Ops,
|
|
bool ReMatLoadSS) const;
|
|
|
|
/// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
|
|
/// VNInfo that's after the specified index but is within the basic block.
|
|
bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
|
|
MachineBasicBlock *MBB,
|
|
MachineInstrIndex Idx) const;
|
|
|
|
/// hasAllocatableSuperReg - Return true if the specified physical register
|
|
/// has any super register that's allocatable.
|
|
bool hasAllocatableSuperReg(unsigned Reg) const;
|
|
|
|
/// SRInfo - Spill / restore info.
|
|
struct SRInfo {
|
|
MachineInstrIndex index;
|
|
unsigned vreg;
|
|
bool canFold;
|
|
SRInfo(MachineInstrIndex i, unsigned vr, bool f)
|
|
: index(i), vreg(vr), canFold(f) {}
|
|
};
|
|
|
|
bool alsoFoldARestore(int Id, MachineInstrIndex index, unsigned vr,
|
|
BitVector &RestoreMBBs,
|
|
DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
|
|
void eraseRestoreInfo(int Id, MachineInstrIndex index, unsigned vr,
|
|
BitVector &RestoreMBBs,
|
|
DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
|
|
|
|
/// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
|
|
/// spilled and create empty intervals for their uses.
|
|
void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
|
|
const TargetRegisterClass* rc,
|
|
std::vector<LiveInterval*> &NewLIs);
|
|
|
|
/// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
|
|
/// interval on to-be re-materialized operands of MI) with new register.
|
|
void rewriteImplicitOps(const LiveInterval &li,
|
|
MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
|
|
|
|
/// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
|
|
/// functions for addIntervalsForSpills to rewrite uses / defs for the given
|
|
/// live range.
|
|
bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
|
|
bool TrySplit, MachineInstrIndex index, MachineInstrIndex end,
|
|
MachineInstr *MI, MachineInstr *OrigDefMI, MachineInstr *DefMI,
|
|
unsigned Slot, int LdSlot,
|
|
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
|
|
VirtRegMap &vrm, const TargetRegisterClass* rc,
|
|
SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
|
|
unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
|
|
DenseMap<unsigned,unsigned> &MBBVRegsMap,
|
|
std::vector<LiveInterval*> &NewLIs);
|
|
void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
|
|
LiveInterval::Ranges::const_iterator &I,
|
|
MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
|
|
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
|
|
VirtRegMap &vrm, const TargetRegisterClass* rc,
|
|
SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
|
|
BitVector &SpillMBBs,
|
|
DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
|
|
BitVector &RestoreMBBs,
|
|
DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
|
|
DenseMap<unsigned,unsigned> &MBBVRegsMap,
|
|
std::vector<LiveInterval*> &NewLIs);
|
|
|
|
static LiveInterval* createInterval(unsigned Reg);
|
|
|
|
void printInstrs(raw_ostream &O) const;
|
|
void dumpInstrs() const;
|
|
};
|
|
} // End llvm namespace
|
|
|
|
#endif
|