mirror of
https://github.com/c64scene-ar/llvm-6502.git
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34a0fa362d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74988 91177308-0d34-0410-b5e6-96231b3b80d8
151 lines
5.7 KiB
C++
151 lines
5.7 KiB
C++
//===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// ARM Subtarget features.
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//
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def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
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"ARM v4T">;
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def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
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"ARM v5T">;
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def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
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"ARM v5TE, v5TEj, v5TExp">;
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def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
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"ARM v6">;
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def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
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"ARM v6t2">;
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def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
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"ARM v7A">;
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def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
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"Enable VFP2 instructions">;
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def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
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"Enable VFP3 instructions">;
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def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
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"Enable NEON instructions">;
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def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
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"Enable Thumb2 instructions">;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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//
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include "ARMSchedule.td"
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class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, GenericItineraries, Features>;
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// V4 Processors.
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def : ProcNoItin<"generic", []>;
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def : ProcNoItin<"arm8", []>;
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def : ProcNoItin<"arm810", []>;
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def : ProcNoItin<"strongarm", []>;
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def : ProcNoItin<"strongarm110", []>;
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def : ProcNoItin<"strongarm1100", []>;
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def : ProcNoItin<"strongarm1110", []>;
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// V4T Processors.
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def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
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def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
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def : ProcNoItin<"arm710t", [ArchV4T]>;
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def : ProcNoItin<"arm720t", [ArchV4T]>;
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def : ProcNoItin<"arm9", [ArchV4T]>;
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def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
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def : ProcNoItin<"arm920", [ArchV4T]>;
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def : ProcNoItin<"arm920t", [ArchV4T]>;
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def : ProcNoItin<"arm922t", [ArchV4T]>;
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def : ProcNoItin<"arm940t", [ArchV4T]>;
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def : ProcNoItin<"ep9312", [ArchV4T]>;
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// V5T Processors.
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def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
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def : ProcNoItin<"arm1020t", [ArchV5T]>;
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// V5TE Processors.
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def : ProcNoItin<"arm9e", [ArchV5TE]>;
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def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
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def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
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def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
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def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
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def : ProcNoItin<"arm10e", [ArchV5TE]>;
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def : ProcNoItin<"arm1020e", [ArchV5TE]>;
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def : ProcNoItin<"arm1022e", [ArchV5TE]>;
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def : ProcNoItin<"xscale", [ArchV5TE]>;
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def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
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// V6 Processors.
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def : Processor<"arm1136j-s", V6Itineraries,
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[ArchV6]>;
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def : Processor<"arm1136jf-s", V6Itineraries,
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[ArchV6, FeatureVFP2]>;
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def : Processor<"arm1176jz-s", V6Itineraries,
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[ArchV6]>;
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def : Processor<"arm1176jzf-s", V6Itineraries,
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[ArchV6, FeatureVFP2]>;
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def : Processor<"mpcorenovfp", V6Itineraries,
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[ArchV6]>;
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def : Processor<"mpcore", V6Itineraries,
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[ArchV6, FeatureVFP2]>;
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// V6T2 Processors.
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def : Processor<"arm1156t2-s", V6Itineraries,
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[ArchV6T2, FeatureThumb2]>;
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def : Processor<"arm1156t2f-s", V6Itineraries,
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[ArchV6T2, FeatureThumb2, FeatureVFP2]>;
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// V7 Processors.
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def : ProcNoItin<"cortex-a8", [ArchV7A, FeatureThumb2, FeatureNEON]>;
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def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "ARMRegisterInfo.td"
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include "ARMCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "ARMInstrInfo.td"
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def ARMInstrInfo : InstrInfo {
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// Define how we want to layout our target-specific information field.
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let TSFlagsFields = ["AddrModeBits",
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"SizeFlag",
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"IndexModeBits",
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"Form",
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"isUnaryDataProc"];
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let TSFlagsShifts = [0,
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4,
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7,
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9,
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15];
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}
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def ARM : Target {
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// Pull in Instruction Info:
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let InstructionSet = ARMInstrInfo;
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}
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