mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
156 lines
5.0 KiB
LLVM
156 lines
5.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; Test expansion of scalar selects on vectors.
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; Evergreen not enabled since it seems to be having problems with doubles.
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; FUNC-LABEL: {{^}}select_v4i8:
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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define void @select_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, <4 x i8> %b, i8 %c) nounwind {
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%cmp = icmp eq i8 %c, 0
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%select = select i1 %cmp, <4 x i8> %a, <4 x i8> %b
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store <4 x i8> %select, <4 x i8> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}select_v4i16:
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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define void @select_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <4 x i16> %a, <4 x i16> %b
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store <4 x i16> %select, <4 x i16> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}select_v2i32:
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: buffer_store_dwordx2
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define void @select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
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store <2 x i32> %select, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}select_v4i32:
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: buffer_store_dwordx4
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define void @select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b
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store <4 x i32> %select, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}select_v8i32:
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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define void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b
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store <8 x i32> %select, <8 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}select_v2f32:
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; SI: buffer_store_dwordx2
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define void @select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <2 x float> %a, <2 x float> %b
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store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}select_v4f32:
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; SI: buffer_store_dwordx4
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define void @select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <4 x float> %a, <4 x float> %b
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store <4 x float> %select, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}select_v8f32:
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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define void @select_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <8 x float> %a, <8 x float> %b
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store <8 x float> %select, <8 x float> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}select_v2f64:
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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define void @select_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <2 x double> %a, <2 x double> %b
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store <2 x double> %select, <2 x double> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}select_v4f64:
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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define void @select_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <4 x double> %a, <4 x double> %b
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store <4 x double> %select, <4 x double> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}select_v8f64:
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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; SI: v_cndmask_b32_e64
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define void @select_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b, i32 %c) nounwind {
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%cmp = icmp eq i32 %c, 0
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%select = select i1 %cmp, <8 x double> %a, <8 x double> %b
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store <8 x double> %select, <8 x double> addrspace(1)* %out, align 16
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ret void
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}
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