Owen Anderson 9ab0f25fc1 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8

2011-08-26 20:43:14 +00:00

..

Analysis

LoopInfo::updateUnloop fix, and verify Block->Loop maps.

2011-08-26 03:06:34 +00:00

Archive

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AsmParser

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Bitcode

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CodeGen

Atomic load/store on ARM/Thumb.

2011-08-26 02:59:24 +00:00

CompilerDriver

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ExecutionEngine

Move TargetRegistry and TargetSelect from Target to Support where they belong.

2011-08-24 18:08:43 +00:00

Linker

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MC

Initialize member variable.

2011-08-25 04:04:18 +00:00

Object

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Support

Intel family 6 model 44 is Gulftown/Westmere-EP and doesn't have AVX.

2011-08-25 18:05:56 +00:00

Target

invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.

2011-08-26 20:43:14 +00:00

Transforms

Don't sink landingpad instructions during ind-var simplification.

2011-08-26 20:40:15 +00:00

VMCore

Initial check in that will auto-upgrade the old EH scheme to the new EH scheme.

2011-08-25 23:22:40 +00:00

CMakeLists.txt

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Makefile

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