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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
141 lines
5.9 KiB
C++
141 lines
5.9 KiB
C++
//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an AArch64 MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AArch64INSTPRINTER_H
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#define AArch64INSTPRINTER_H
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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namespace llvm {
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class MCOperand;
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class AArch64InstPrinter : public MCInstPrinter {
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public:
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AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
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void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
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void printRegName(raw_ostream &OS, unsigned RegNo) const override;
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// Autogenerated by tblgen.
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virtual void printInstruction(const MCInst *MI, raw_ostream &O);
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virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
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virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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unsigned PrintMethodIdx, raw_ostream &O);
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virtual StringRef getRegName(unsigned RegNo) const {
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return getRegisterName(RegNo);
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}
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static const char *getRegisterName(unsigned RegNo,
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unsigned AltIdx = AArch64::NoRegAltName);
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protected:
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bool printSysAlias(const MCInst *MI, raw_ostream &O);
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// Operand printers
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
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raw_ostream &O);
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template<int Amount>
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void printPostIncOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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printPostIncOperand(MI, OpNo, Amount, O);
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}
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void printVRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printSysCROperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printAddSubImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printLogicalImm32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printLogicalImm64(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printShifter(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printShiftedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printArithExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O,
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char SrcRegKind, unsigned Width);
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template <char SrcRegKind, unsigned Width>
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void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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}
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void printCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printInverseCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printAlignedLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale,
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raw_ostream &O);
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void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
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raw_ostream &O);
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template<int Scale>
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void printUImm12Offset(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printUImm12Offset(MI, OpNum, Scale, O);
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}
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template<int BitWidth>
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void printAMIndexedWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
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}
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void printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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template<int Scale>
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void printImmScale(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printPrefetchOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O,
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StringRef LayoutSuffix);
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/// Print a list of vector registers where the type suffix is implicit
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/// (i.e. attached to the instruction rather than the registers).
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void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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template <unsigned NumLanes, char LaneKind>
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void printTypedVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printAdrpLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printBarrierOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printSystemPStateField(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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};
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class AArch64AppleInstPrinter : public AArch64InstPrinter {
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public:
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AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
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void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
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void printInstruction(const MCInst *MI, raw_ostream &O) override;
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bool printAliasInstr(const MCInst *MI, raw_ostream &O) override;
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virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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unsigned PrintMethodIdx, raw_ostream &O);
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StringRef getRegName(unsigned RegNo) const override {
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return getRegisterName(RegNo);
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}
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static const char *getRegisterName(unsigned RegNo,
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unsigned AltIdx = AArch64::NoRegAltName);
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};
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}
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#endif
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