Matt Arsenault 3cd8cf6bbd R600/SI: Add FP mode bits to binary. ...

The default rounding mode to initialize the mode register needs
to be reported to the runtime. Fill in other bits a kernel
may be interested in setting for future use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211791 91177308-0d34-0410-b5e6-96231b3b80d8

2014-06-26 17:22:30 +00:00

..

AArch64

Resubmit commit r211533

2014-06-24 16:21:38 +00:00

ARM

Fix up scoping in a few tests (and delete one that validates unnecessary behavior).

2014-06-24 20:10:27 +00:00

CPP

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Generic

Add a new attribute called 'jumptable' that creates jump-instruction tables for functions marked with this attribute.

2014-06-05 19:29:43 +00:00

Hexagon

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00

Inputs

…

Mips

Print a=b as an assignment.

2014-06-24 22:45:16 +00:00

MSP430

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00

NVPTX

Canonicalize addrspacecast ConstExpr between different pointer types

2014-06-15 21:40:57 +00:00

PowerPC

Rename loop unrolling and loop vectorizer metadata to have a common prefix.

2014-06-25 15:41:00 +00:00

R600

R600/SI: Add FP mode bits to binary.

2014-06-26 17:22:30 +00:00

SPARC

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

SystemZ

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Thumb

ARM: Fix fastcc calling convention for Thumb1

2014-06-13 08:33:03 +00:00

Thumb2

ARM: Fix TPsoft for Thumb mode

2014-06-24 15:45:59 +00:00

X86

[X86] Improve the selection of SSE3/AVX addsub instructions.

2014-06-26 10:45:21 +00:00

XCore

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00