Evan Cheng 9b88d2d782 Tighten a ARM dag combine condition to avoid an identity transformation, which ...

ends up introducing a cycle in the DAG.

rdar://10196296


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8

2011-09-28 23:16:31 +00:00

..

Alpha

Convert more tests over to the new atomic instructions.

2011-09-26 21:30:17 +00:00

ARM

Tighten a ARM dag combine condition to avoid an identity transformation, which

2011-09-28 23:16:31 +00:00

Blackfin

more tests not making the jump into the brave new world.

2011-07-09 16:57:10 +00:00

CBackend

Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported

2011-09-26 06:44:27 +00:00

CellSPU

Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.

2011-09-02 10:05:01 +00:00

CPP

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Generic

PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval

2011-09-26 06:13:20 +00:00

MBlaze

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Mips

Convert more tests over to the new atomic instructions.

2011-09-26 20:27:49 +00:00

MSP430

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PowerPC

Convert more tests over to the new atomic instructions.

2011-09-26 21:30:17 +00:00

PTX

PTX: MC-ize the PTX back-end (patch 1 of N)

2011-09-28 14:32:04 +00:00

SPARC

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SystemZ

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Thumb

Convert more tests to new atomic instructions.

2011-09-26 21:36:10 +00:00

Thumb2

Last batch of test conversions to new atomic instructions.

2011-09-27 00:17:29 +00:00

X86

PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.

2011-09-28 21:00:25 +00:00

XCore

Associate a MemOperand with LDWCP nodes introduced during ISel.

2011-09-12 14:43:23 +00:00