mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ba8297ec08
Move the target-specific RecordRelocation logic out of the generic MC MachObjectWriter and into the target-specific object writers. This allows nuking quite a bit of target knowledge from the supposedly target-independent bits in lib/MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133844 91177308-0d34-0410-b5e6-96231b3b80d8
124 lines
4.0 KiB
C++
124 lines
4.0 KiB
C++
//===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetAsmBackend.h"
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#include "PPC.h"
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#include "PPCFixupKinds.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Object/MachOFormat.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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namespace {
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class PPCMachObjectWriter : public MCMachObjectTargetWriter {
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public:
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PPCMachObjectWriter(bool Is64Bit, uint32_t CPUType,
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uint32_t CPUSubtype)
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: MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {}
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void RecordRelocation(MachObjectWriter *Writer,
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const MCAssembler &Asm, const MCAsmLayout &Layout,
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const MCFragment *Fragment, const MCFixup &Fixup,
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MCValue Target, uint64_t &FixedValue) {}
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};
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class PPCAsmBackend : public TargetAsmBackend {
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const Target &TheTarget;
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public:
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PPCAsmBackend(const Target &T) : TargetAsmBackend(), TheTarget(T) {}
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unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; }
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[PPC::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_lo16", 16, 16, 0 },
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{ "fixup_ppc_ha16", 16, 16, 0 },
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{ "fixup_ppc_lo14", 16, 14, 0 }
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};
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if (Kind < FirstTargetFixupKind)
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return TargetAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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bool MayNeedRelaxation(const MCInst &Inst) const {
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// FIXME.
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return false;
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}
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void RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
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// FIXME.
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assert(0 && "RelaxInstruction() unimplemented");
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}
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bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
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// FIXME: Zero fill for now. That's not right, but at least will get the
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// section size right.
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for (uint64_t i = 0; i != Count; ++i)
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OW->Write8(0);
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return true;
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}
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unsigned getPointerSize() const {
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StringRef Name = TheTarget.getName();
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if (Name == "ppc64") return 8;
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assert(Name == "ppc32" && "Unknown target name!");
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return 4;
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}
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};
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} // end anonymous namespace
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// FIXME: This should be in a separate file.
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namespace {
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class DarwinPPCAsmBackend : public PPCAsmBackend {
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public:
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DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T) { }
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void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const {
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assert(0 && "UNIMP");
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}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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bool is64 = getPointerSize() == 8;
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return createMachObjectWriter(new PPCMachObjectWriter(
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/*Is64Bit=*/is64,
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(is64 ? object::mach::CTM_PowerPC64 :
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object::mach::CTM_PowerPC),
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object::mach::CSPPC_ALL),
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OS, /*IsLittleEndian=*/false);
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}
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virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
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return false;
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}
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};
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} // end anonymous namespace
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TargetAsmBackend *llvm::createPPCAsmBackend(const Target &T,
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const std::string &TT) {
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if (Triple(TT).isOSDarwin())
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return new DarwinPPCAsmBackend(T);
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return 0;
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}
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