Gerolf Hoflehner 2bddd7cf65 [AAarch64] Optimize CSINC-branch sequence ... Peephole optimization that generates a single conditional branch for csinc-branch sequences like in the examples below. This is possible when the csinc sets or clears a register based on a condition code and the branch checks that register. Also the condition code may not be modified between the csinc and the original branch. Examples: 1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44 to b.<invCC> 2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44 to b.<CC> rdar://problem/18506500 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219742 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-14 23:07:53 +00:00
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CostTable.h
Target.td	Remove unused field from Operand	2014-10-09 19:15:18 +00:00
TargetCallingConv.h
TargetCallingConv.td	[mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and handle struct's correctly on big-endian N32/N64 return values.	2014-09-25 12:15:05 +00:00
TargetFrameLowering.h
TargetInstrInfo.h	[AAarch64] Optimize CSINC-branch sequence	2014-10-14 23:07:53 +00:00
TargetIntrinsicInfo.h
TargetItinerary.td
TargetLibraryInfo.h	PR21145: Teach LLVM about C++14 sized deallocation functions.	2014-10-03 20:17:06 +00:00
TargetLowering.h	[DAGCombine] Remove SIGN_EXTEND-related inf-loop	2014-10-06 20:19:47 +00:00
TargetLoweringObjectFile.h
TargetMachine.h	Target: Fix build breakage.	2014-09-26 02:57:05 +00:00
TargetOpcodes.h	[stack protector] Fix a potential security bug in stack protector where the	2014-07-25 19:31:34 +00:00
TargetOptions.h	Satiate the sanitizer build bot	2014-08-21 20:09:15 +00:00
TargetRegisterInfo.h	Revert 202433 - Provide a target override for the latest regalloc heuristic	2014-10-03 12:20:53 +00:00
TargetSchedule.td
TargetSelectionDAG.td	Add SDAG TableGen definitions for BR_CC	2014-09-25 23:34:18 +00:00
TargetSelectionDAGInfo.h
TargetSubtargetInfo.h	[PBQP] Replace PBQPBuilder with composable constraints (PBQPRAConstraint).	2014-10-09 18:20:51 +00:00