Evan Cheng c38f2bc3c2 - Reorg Thumb load / store instructions. Combine each rr and ri pair of ...

instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
  address is not an add, materialize a 0 immediate into a register and use
  it as the offset field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33470 91177308-0d34-0410-b5e6-96231b3b80d8

2007-01-23 22:59:13 +00:00

..

Analysis

Fix typo.

2007-01-23 21:55:17 +00:00

Archive

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AsmParser

Fix this error:

2007-01-21 19:19:31 +00:00

Bytecode

Back out last changes for dataLayout. Much more work is needed.

2007-01-19 00:07:16 +00:00

CodeGen

PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary.

2007-01-23 09:38:11 +00:00

Debugger

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ExecutionEngine

Moved disassembler to libSystem

2007-01-23 10:26:08 +00:00

Linker

For PR1064:

2007-01-12 07:05:14 +00:00

Support

Moved disassembler to libSystem

2007-01-23 10:26:08 +00:00

System

Moved disassembler to libSystem

2007-01-23 10:26:08 +00:00

Target

- Reorg Thumb load / store instructions. Combine each rr and ri pair of

2007-01-23 22:59:13 +00:00

Transforms

Cleanup checks in the load and store of casted pointer transforms. Two

2007-01-22 05:51:25 +00:00

VMCore

Whoops, fix typo in last commit.

2007-01-21 02:29:10 +00:00

Makefile

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