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c72c617a4e
compile on windows. This patch was contributed by Paolo Invernizzi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16539 91177308-0d34-0410-b5e6-96231b3b80d8
430 lines
14 KiB
C++
430 lines
14 KiB
C++
//===-- MSchedGraph.cpp - Scheduling Graph ----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// A graph class for dependencies
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "ModuloSched"
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#include "MSchedGraph.h"
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#include "../../Target/SparcV9/SparcV9RegisterInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include <cstdlib>
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#include <algorithm>
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using namespace llvm;
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MSchedGraphNode::MSchedGraphNode(const MachineInstr* inst,
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MSchedGraph *graph,
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unsigned late, bool isBranch)
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: Inst(inst), Parent(graph), latency(late), isBranchInstr(isBranch) {
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//Add to the graph
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graph->addNode(inst, this);
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}
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void MSchedGraphNode::print(std::ostream &os) const {
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os << "MSchedGraphNode: Inst=" << *Inst << ", latency= " << latency << "\n";
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}
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MSchedGraphEdge MSchedGraphNode::getInEdge(MSchedGraphNode *pred) {
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//Loop over all the successors of our predecessor
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//return the edge the corresponds to this in edge
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for (MSchedGraphNode::succ_iterator I = pred->succ_begin(),
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E = pred->succ_end(); I != E; ++I) {
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if (*I == this)
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return I.getEdge();
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}
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assert(0 && "Should have found edge between this node and its predecessor!");
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abort();
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}
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unsigned MSchedGraphNode::getInEdgeNum(MSchedGraphNode *pred) {
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//Loop over all the successors of our predecessor
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//return the edge the corresponds to this in edge
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int count = 0;
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for(MSchedGraphNode::succ_iterator I = pred->succ_begin(), E = pred->succ_end();
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I != E; ++I) {
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if(*I == this)
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return count;
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count++;
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}
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assert(0 && "Should have found edge between this node and its predecessor!");
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abort();
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}
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bool MSchedGraphNode::isSuccessor(MSchedGraphNode *succ) {
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for(succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
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if(*I == succ)
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return true;
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return false;
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}
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bool MSchedGraphNode::isPredecessor(MSchedGraphNode *pred) {
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if(std::find( Predecessors.begin(), Predecessors.end(), pred) != Predecessors.end())
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return true;
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else
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return false;
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}
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void MSchedGraph::addNode(const MachineInstr *MI,
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MSchedGraphNode *node) {
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//Make sure node does not already exist
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assert(GraphMap.find(MI) == GraphMap.end()
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&& "New MSchedGraphNode already exists for this instruction");
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GraphMap[MI] = node;
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}
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MSchedGraph::MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ)
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: BB(bb), Target(targ) {
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//Make sure BB is not null,
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assert(BB != NULL && "Basic Block is null");
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DEBUG(std::cerr << "Constructing graph for " << bb << "\n");
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//Create nodes and edges for this BB
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buildNodesAndEdges();
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}
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MSchedGraph::~MSchedGraph () {
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for(MSchedGraph::iterator I = GraphMap.begin(), E = GraphMap.end(); I != E; ++I)
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delete I->second;
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}
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void MSchedGraph::buildNodesAndEdges() {
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//Get Machine target information for calculating latency
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const TargetInstrInfo *MTI = Target.getInstrInfo();
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std::vector<MSchedGraphNode*> memInstructions;
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std::map<int, std::vector<OpIndexNodePair> > regNumtoNodeMap;
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std::map<const Value*, std::vector<OpIndexNodePair> > valuetoNodeMap;
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//Save PHI instructions to deal with later
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std::vector<const MachineInstr*> phiInstrs;
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//Loop over instructions in MBB and add nodes and edges
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for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end(); MI != e; ++MI) {
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//Get each instruction of machine basic block, get the delay
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//using the op code, create a new node for it, and add to the
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//graph.
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MachineOpCode opCode = MI->getOpcode();
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int delay;
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#if 0 // FIXME: LOOK INTO THIS
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//Check if subsequent instructions can be issued before
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//the result is ready, if so use min delay.
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if(MTI->hasResultInterlock(MIopCode))
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delay = MTI->minLatency(MIopCode);
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else
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#endif
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//Get delay
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delay = MTI->maxLatency(opCode);
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//Create new node for this machine instruction and add to the graph.
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//Create only if not a nop
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if(MTI->isNop(opCode))
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continue;
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//Add PHI to phi instruction list to be processed later
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if (opCode == TargetInstrInfo::PHI)
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phiInstrs.push_back(MI);
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bool isBranch = false;
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//We want to flag the branch node to treat it special
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if(MTI->isBranch(opCode))
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isBranch = true;
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//Node is created and added to the graph automatically
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MSchedGraphNode *node = new MSchedGraphNode(MI, this, delay, isBranch);
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DEBUG(std::cerr << "Created Node: " << *node << "\n");
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//Check OpCode to keep track of memory operations to add memory dependencies later.
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if(MTI->isLoad(opCode) || MTI->isStore(opCode))
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memInstructions.push_back(node);
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//Loop over all operands, and put them into the register number to
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//graph node map for determining dependencies
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//If an operands is a use/def, we have an anti dependence to itself
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for(unsigned i=0; i < MI->getNumOperands(); ++i) {
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//Get Operand
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const MachineOperand &mOp = MI->getOperand(i);
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//Check if it has an allocated register
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if(mOp.hasAllocatedReg()) {
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int regNum = mOp.getReg();
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if(regNum != SparcV9::g0) {
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//Put into our map
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regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
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}
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continue;
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}
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//Add virtual registers dependencies
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//Check if any exist in the value map already and create dependencies
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//between them.
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if(mOp.getType() == MachineOperand::MO_VirtualRegister || mOp.getType() == MachineOperand::MO_CCRegister) {
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//Make sure virtual register value is not null
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assert((mOp.getVRegValue() != NULL) && "Null value is defined");
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//Check if this is a read operation in a phi node, if so DO NOT PROCESS
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if(mOp.isUse() && (opCode == TargetInstrInfo::PHI))
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continue;
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if (const Value* srcI = mOp.getVRegValue()) {
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//Find value in the map
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std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
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= valuetoNodeMap.find(srcI);
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//If there is something in the map already, add edges from
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//those instructions
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//to this one we are processing
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if(V != valuetoNodeMap.end()) {
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addValueEdges(V->second, node, mOp.isUse(), mOp.isDef());
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//Add to value map
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V->second.push_back(std::make_pair(i,node));
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}
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//Otherwise put it in the map
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else
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//Put into value map
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valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
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}
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}
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}
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}
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addMemEdges(memInstructions);
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addMachRegEdges(regNumtoNodeMap);
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//Finally deal with PHI Nodes and Value*
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for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(), E = phiInstrs.end(); I != E; ++I) {
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//Get Node for this instruction
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MSchedGraphNode *node = find(*I)->second;
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//Loop over operands for this instruction and add value edges
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for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
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//Get Operand
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const MachineOperand &mOp = (*I)->getOperand(i);
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if((mOp.getType() == MachineOperand::MO_VirtualRegister || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
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//find the value in the map
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if (const Value* srcI = mOp.getVRegValue()) {
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//Find value in the map
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std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
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= valuetoNodeMap.find(srcI);
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//If there is something in the map already, add edges from
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//those instructions
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//to this one we are processing
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if(V != valuetoNodeMap.end()) {
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addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), 1);
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}
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}
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}
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}
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}
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}
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void MSchedGraph::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
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MSchedGraphNode *destNode, bool nodeIsUse,
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bool nodeIsDef, int diff) {
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for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
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E = NodesInMap.end(); I != E; ++I) {
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//Get node in vectors machine operand that is the same value as node
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MSchedGraphNode *srcNode = I->second;
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MachineOperand mOp = srcNode->getInst()->getOperand(I->first);
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//Node is a Def, so add output dep.
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if(nodeIsDef) {
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if(mOp.isUse())
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srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
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MSchedGraphEdge::AntiDep, diff);
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if(mOp.isDef())
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srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
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MSchedGraphEdge::OutputDep, diff);
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}
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if(nodeIsUse) {
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if(mOp.isDef())
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srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
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MSchedGraphEdge::TrueDep, diff);
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}
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}
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}
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void MSchedGraph::addMachRegEdges(std::map<int, std::vector<OpIndexNodePair> >& regNumtoNodeMap) {
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//Loop over all machine registers in the map, and add dependencies
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//between the instructions that use it
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typedef std::map<int, std::vector<OpIndexNodePair> > regNodeMap;
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for(regNodeMap::iterator I = regNumtoNodeMap.begin(); I != regNumtoNodeMap.end(); ++I) {
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//Get the register number
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int regNum = (*I).first;
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//Get Vector of nodes that use this register
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std::vector<OpIndexNodePair> Nodes = (*I).second;
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//Loop over nodes and determine the dependence between the other
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//nodes in the vector
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for(unsigned i =0; i < Nodes.size(); ++i) {
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//Get src node operator index that uses this machine register
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int srcOpIndex = Nodes[i].first;
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//Get the actual src Node
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MSchedGraphNode *srcNode = Nodes[i].second;
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//Get Operand
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const MachineOperand &srcMOp = srcNode->getInst()->getOperand(srcOpIndex);
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bool srcIsUseandDef = srcMOp.isDef() && srcMOp.isUse();
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bool srcIsUse = srcMOp.isUse() && !srcMOp.isDef();
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//Look at all instructions after this in execution order
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for(unsigned j=i+1; j < Nodes.size(); ++j) {
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//Sink node is a write
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if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
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//Src only uses the register (read)
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if(srcIsUse)
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srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
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MSchedGraphEdge::AntiDep);
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else if(srcIsUseandDef) {
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srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
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MSchedGraphEdge::AntiDep);
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srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
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MSchedGraphEdge::OutputDep);
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}
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else
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srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
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MSchedGraphEdge::OutputDep);
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}
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//Dest node is a read
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else {
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if(!srcIsUse || srcIsUseandDef)
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srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
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MSchedGraphEdge::TrueDep);
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}
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}
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//Look at all the instructions before this one since machine registers
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//could live across iterations.
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for(unsigned j = 0; j < i; ++j) {
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//Sink node is a write
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if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
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//Src only uses the register (read)
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if(srcIsUse)
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srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
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MSchedGraphEdge::AntiDep, 1);
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else if(srcIsUseandDef) {
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srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
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MSchedGraphEdge::AntiDep, 1);
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srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
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MSchedGraphEdge::OutputDep, 1);
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}
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else
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srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
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MSchedGraphEdge::OutputDep, 1);
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}
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//Dest node is a read
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else {
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if(!srcIsUse || srcIsUseandDef)
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srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
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MSchedGraphEdge::TrueDep,1 );
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}
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}
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}
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}
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}
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void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst) {
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//Get Target machine instruction info
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const TargetInstrInfo *TMI = Target.getInstrInfo();
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//Loop over all memory instructions in the vector
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//Knowing that they are in execution, add true, anti, and output dependencies
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for (unsigned srcIndex = 0; srcIndex < memInst.size(); ++srcIndex) {
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//Get the machine opCode to determine type of memory instruction
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MachineOpCode srcNodeOpCode = memInst[srcIndex]->getInst()->getOpcode();
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//All instructions after this one in execution order have an iteration delay of 0
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for(unsigned destIndex = srcIndex + 1; destIndex < memInst.size(); ++destIndex) {
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//source is a Load, so add anti-dependencies (store after load)
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if(TMI->isLoad(srcNodeOpCode))
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::AntiDep);
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//If source is a store, add output and true dependencies
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if(TMI->isStore(srcNodeOpCode)) {
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::OutputDep);
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else
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::TrueDep);
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}
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}
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//All instructions before the src in execution order have an iteration delay of 1
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for(unsigned destIndex = 0; destIndex < srcIndex; ++destIndex) {
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//source is a Load, so add anti-dependencies (store after load)
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if(TMI->isLoad(srcNodeOpCode))
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::AntiDep, 1);
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if(TMI->isStore(srcNodeOpCode)) {
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::OutputDep, 1);
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else
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::TrueDep, 1);
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}
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}
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}
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}
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