James Molloy 873fd5f753 Improve generated code for extending loads and some trunc stores on ARM. ... Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150956 91177308-0d34-0410-b5e6-96231b3b80d8		2012-02-20 09:24:05 +00:00
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Mangler.h
Target.td	Specify SubRegIndex components on the index itself.	2012-02-01 23:16:41 +00:00
TargetCallingConv.h	Minimize #include's and forward-declares in Target.	2011-12-10 22:35:47 +00:00
TargetCallingConv.td	Add TableGen support for callee saved registers.	2012-01-17 22:46:58 +00:00
TargetData.h
TargetELFWriterInfo.h
TargetFrameLowering.h
TargetInstrInfo.h	Convert assert(0) to llvm_unreachable	2012-02-05 22:14:15 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h	Convert assert(0) to llvm_unreachable	2012-02-05 22:14:15 +00:00
TargetLibraryInfo.h	Remove redundant getAnalysis<> calls in GlobalOpt. Add a few Itanium ABI calls	2012-02-12 02:15:20 +00:00
TargetLowering.h	Rename getExceptionAddressRegister() to getExceptionPointerRegister() for consistency with setExceptionPointerRegister(...).	2012-02-14 04:45:49 +00:00
TargetLoweringObjectFile.h	Modify the code that emits the module flags to use the new module flags accessor	2012-02-15 22:36:15 +00:00
TargetMachine.h	TargetPassConfig: confine the MC configuration to TargetMachine.	2012-02-04 02:56:59 +00:00
TargetOpcodes.h
TargetOptions.h	RegAlloc superpass: includes phi elimination, coalescing, and scheduling.	2012-02-10 04:10:36 +00:00
TargetRegisterInfo.h	Store just the SimpleValueType in the generated VT tables for each register class, eliminating static ctors.	2012-02-09 12:35:37 +00:00
TargetSchedule.td
TargetSelectionDAG.td	Improve generated code for extending loads and some trunc stores on ARM.	2012-02-20 09:24:05 +00:00
TargetSelectionDAGInfo.h
TargetSubtargetInfo.h