David Goodwin dc4bdcdef1 Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79425 91177308-0d34-0410-b5e6-96231b3b80d8

2009-08-19 16:08:58 +00:00

..

COFFTargetAsmInfo.h

remove TargetAsmInfo::TM, which is now dead. The basic TAI class now

2009-08-02 04:27:24 +00:00

DarwinTargetAsmInfo.h

Revert 78892 and 78895, these break generating working executables on

2009-08-13 17:03:38 +00:00

SubtargetFeature.h

Propagate CPU string out of SubtargetFeatures

2009-05-23 19:50:50 +00:00

Target.td

Add 'isCodeGenOnly' bit to Instruction .td records.

2009-08-11 22:17:52 +00:00

TargetAsmInfo.h

Remove HasCrazyBSS and add a flag in TAI to indicate that '.section'

2009-08-13 23:30:21 +00:00

TargetAsmParser.h

Move X86 instruction parsing into X86/AsmParser.

2009-07-28 22:40:46 +00:00

TargetCallingConv.td

Add 'Indirect' LocInfo class and use to pass __m128 on win64. Also minore fixes here and there (mostly __m64).

2009-08-03 08:13:56 +00:00

TargetData.h

Push LLVMContexts through the IntegerType APIs.

2009-08-13 21:58:54 +00:00

TargetELFWriterInfo.h

- Remove custom handling of jumptables by the elf writter (this was

2009-08-05 06:57:03 +00:00

TargetFrameInfo.h

…

TargetInstrDesc.h

1. Introduce a new TargetOperandInfo::getRegClass() helper method

2009-07-29 21:10:12 +00:00

TargetInstrInfo.h

Move the getInlineAsmLength virtual method from TAI to TII, where

2009-08-02 05:20:37 +00:00

TargetInstrItineraries.h

Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.

2009-08-19 16:08:58 +00:00

TargetIntrinsicInfo.h

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TargetJITInfo.h

First patch in the direction of splitting MachineCodeEmitter in two subclasses:

2009-05-30 20:51:52 +00:00

TargetLowering.h

Reapply r79127. It was fixed by d0k.

2009-08-15 21:21:19 +00:00

TargetLoweringObjectFile.h

Remove HasCrazyBSS and add a flag in TAI to indicate that '.section'

2009-08-13 23:30:21 +00:00

TargetMachine.h

Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple

2009-08-12 07:22:17 +00:00

TargetMachOWriterInfo.h

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TargetOptions.h

SjLj based exception handling unwinding support. This patch is nasty, brutish

2009-08-11 00:09:57 +00:00

TargetRegisterInfo.h

Split EVT into MVT and EVT, the former representing _just_ a primitive type, while

2009-08-11 20:47:22 +00:00

TargetRegistry.h

TargetRegistry: Change AsmPrinter constructor to be typed as returning an

2009-08-13 23:48:47 +00:00

TargetSchedule.td

Extend the instruction itinerary model to include the ability to indicate the def and use cycle for each operand. This additional information is optional, so existing itineraries do not need to be changed.

2009-08-17 16:02:57 +00:00

TargetSelect.h

Add llvm::InitializeAllTargetInfos and llvm::InitializeAllAsmParsers.

2009-07-17 22:35:35 +00:00

TargetSelectionDAG.td

Add a new "SDTCisVec" SDTypeConstraint. This complements the vAny type.

2009-08-12 22:30:59 +00:00

TargetSubtarget.h

Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.

2009-08-19 16:08:58 +00:00