Stuart Hastings 865f09334f Reapply 132424 with fixes. This fixes PR10068. ...

rdar://problem/5993888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132606 91177308-0d34-0410-b5e6-96231b3b80d8

2011-06-03 23:53:54 +00:00

..

Alpha

…

ARM

Another possible bug. Stopgap until we can autogenerate tables and

2011-06-03 22:09:12 +00:00

Blackfin

Don't completely eliminate identity copies that also modify super register liveness.

2011-03-31 17:55:25 +00:00

CBackend

…

CellSPU

don't test for codegen of 'store undef'

2011-04-09 02:31:26 +00:00

CPP

…

Generic

This patch is another step in the direction of adding vector select. In this

2011-06-01 12:51:46 +00:00

MBlaze

Add scheduling information for the MBlaze backend.

2011-04-11 22:31:52 +00:00

Mips

Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.

2011-06-02 01:03:14 +00:00

MSP430

Fix register-dependent test in MSP430.

2011-05-04 01:01:39 +00:00

PowerPC

Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.

2011-06-03 15:47:49 +00:00

PTX

PTX: add flag to disable mad/fma selection

2011-05-18 15:42:23 +00:00

SPARC

Fix more register and coalescing dependencies.

2011-05-04 19:02:11 +00:00

SystemZ

Fix SystemZ tests

2011-03-31 23:02:12 +00:00

Thumb

Move this test to CodeGen/Thumb. rdar://problem/9416774

2011-05-11 19:41:28 +00:00

Thumb2

Switch AllocationOrder to using RegisterClassInfo instead of a BitVector

2011-06-03 20:34:53 +00:00

X86

Reapply 132424 with fixes. This fixes PR10068.

2011-06-03 23:53:54 +00:00

XCore

Add XCore intrinsic for crc8.

2011-05-31 16:24:49 +00:00