Silviu Baranga a0c48eb8f6 Added soft fail cases for the disassembler when decoding MUL instructions on ARM. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8

2012-03-22 13:14:39 +00:00

..

arm-tests.txt

ARM VLDR/VSTR instructions don't need a size suffix.

2011-11-14 23:03:21 +00:00

basic-arm-instructions.txt

…

fp-encoding.txt

ARM VLDR/VSTR instructions don't need a size suffix.

2011-11-14 23:03:21 +00:00

invalid-Bcc-thumb.txt

…

invalid-BFI-arm.txt

…

invalid-CPS2p-arm.txt

…

invalid-CPS3p-arm.txt

…

invalid-DMB-thumb.txt

…

invalid-DSB-arm.txt

…

invalid-IT-CBNZ-thumb.txt

…

invalid-IT-CC15.txt

Change ARMInstPrinter::printPredicateOperand() so it will not abort if it

2012-03-01 22:13:02 +00:00

invalid-IT-thumb.txt

…

invalid-LDC-form-arm.txt

…

invalid-LDM-thumb.txt

…

invalid-LDR_POST-arm.txt

…

invalid-LDR_PRE-arm.txt

…

invalid-LDRB_POST-arm.txt

…

invalid-LDRD_PRE-thumb.txt

…

invalid-LDRD-arm.txt

…

invalid-LDRrs-arm.txt

…

invalid-LDRT-arm.txt

…

invalid-MCR-arm.txt

…

invalid-MOVr-arm.txt

…

invalid-MOVs-arm.txt

…

invalid-MOVs-LSL-arm.txt

…

invalid-MOVTi16-arm.txt

…

invalid-MSRi-arm.txt

…

invalid-RFEorLDMIA-arm.txt

…

invalid-SBFX-arm.txt

…

invalid-SMLAD-arm.txt

…

invalid-SRS-arm.txt

…

invalid-STMIA_UPD-thumb.txt

…

invalid-SXTB-arm.txt

…

invalid-t2Bcc-thumb.txt

…

invalid-t2LDRBT-thumb.txt

…

invalid-t2LDREXD-thumb.txt

…

invalid-t2LDRSHi8-thumb.txt

…

invalid-t2LDRSHi12-thumb.txt

…

invalid-t2PUSH-thumb.txt

…

invalid-t2STR_POST-thumb.txt

…

invalid-t2STRD_PRE-thumb.txt

…

invalid-t2STREXB-thumb.txt

…

invalid-t2STREXD-thumb.txt

…

invalid-UMAAL-arm.txt

…

invalid-VLD1DUPq8_UPD-arm.txt

…

invalid-VLD3DUPd32_UPD-thumb.txt

…

invalid-VLDMSDB_UPD-arm.txt

…

invalid-VQADD-arm.txt

…

invalid-VST2b32_UPD-arm.txt

…

lit.local.cfg

Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.

2012-02-16 06:28:33 +00:00

memory-arm-instructions.txt

…

neon-tests.txt

Simplify some uses of utohexstr.

2011-11-07 21:00:59 +00:00

neon.txt

Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test

2012-03-21 20:54:32 +00:00

neont2.txt

Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test

2012-03-21 20:54:32 +00:00

thumb1.txt

…

thumb2.txt

…

thumb-MSR-MClass.txt

…

thumb-printf.txt

…

thumb-tests.txt

…

unpredictable-LSL-regform.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictable-MUL-arm.txt

Added soft fail cases for the disassembler when decoding MUL instructions on ARM.

2012-03-22 13:14:39 +00:00

unpredictable-RSC-arm.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictable-SSAT-arm.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictable-STRBrs-arm.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictable-UQADD8-arm.txt

The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

2012-03-20 15:54:56 +00:00

unpredictables-thumb.txt

Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.

2012-02-09 10:56:31 +00:00