Akira Hatanaka 44b6c715ac Add support for floating point base register + offset register addressing mode ... load and store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8		2012-02-28 02:55:02 +00:00
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ARM	Handle regmasks in MachineCSE.	2012-02-28 02:08:50 +00:00
CBackend
CellSPU
CPP
Generic
Hexagon
MBlaze
Mips	Add support for floating point base register + offset register addressing mode	2012-02-28 02:55:02 +00:00
MSP430
PowerPC	Test the section specification.	2012-02-27 20:42:19 +00:00
PTX
SPARC
Thumb
Thumb2	Enable ARM base pointer when calling functions with large arguments.	2012-02-28 01:15:01 +00:00
X86	test commit.	2012-02-27 23:31:51 +00:00
XCore