Jack Carter b8145e3881 Mips assembler: Explicit floating point condition register recognition. ...

This patch allows the assembler to recognize $fcc0 
as a valid register for conditional move instructions. 

Corresponding test cases have been added.

Contributer: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8

2013-04-15 22:21:55 +00:00

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do_switch.ll

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eh-frame.s

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elf_basic.s

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elf_eflags.ll

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elf_st_other.ll

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elf-bigendian.ll

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elf-gprel-32-64.ll

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elf-N64.ll

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elf-objdump.s

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elf-reginfo.ll

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elf-relsym.ll

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elf-tls.ll

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higher_highest.ll

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hilo-addressing.s

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lea_64.ll

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lit.local.cfg

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mips64-alu-instructions.s

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mips64-register-names.s

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mips64extins.ll

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mips64shift.ll

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mips_directives.s

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mips_gprel16.ll

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mips-alu-instructions.s

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mips-coprocessor-encodings.s

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mips-expansions.s

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mips-fpu-instructions.s

Mips assembler: Explicit floating point condition register recognition.

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mips-jump-instructions.s

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mips-memory-instructions.s

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mips-register-names.s

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mips-relocations.s

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multi-64bit-func.ll

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nabi-regs.s

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pr11877.s

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r-mips-got-disp.ll

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set-at-directive.s

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sext_64_32.ll

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sym-offset.ll

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xgot.ll

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