mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e11fb34381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43249 91177308-0d34-0410-b5e6-96231b3b80d8
249 lines
8.3 KiB
C++
249 lines
8.3 KiB
C++
//===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Christopher Lamb and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "lowersubregs"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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using namespace llvm;
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namespace {
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struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
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: public MachineFunctionPass {
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static char ID; // Pass identification, replacement for typeid
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LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
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const char *getPassName() const {
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return "Subregister lowering instruction pass";
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}
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/// runOnMachineFunction - pass entry point
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bool runOnMachineFunction(MachineFunction&);
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bool LowerExtract(MachineInstr *MI);
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bool LowerInsert(MachineInstr *MI);
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};
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char LowerSubregsInstructionPass::ID = 0;
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}
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FunctionPass *llvm::createLowerSubregsPass() {
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return new LowerSubregsInstructionPass();
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}
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// Returns the Register Class of a physical register.
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static const TargetRegisterClass *getPhysicalRegisterRegClass(
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const MRegisterInfo &MRI,
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unsigned reg) {
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assert(MRegisterInfo::isPhysicalRegister(reg) &&
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"reg must be a physical register");
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// Pick the register class of the right type that contains this physreg.
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for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
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E = MRI.regclass_end(); I != E; ++I)
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if ((*I)->contains(reg))
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return *I;
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assert(false && "Couldn't find the register class");
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return 0;
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}
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bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction &MF = *MBB->getParent();
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const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
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assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
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MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
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MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
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unsigned SuperReg = MI->getOperand(1).getReg();
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unsigned SubIdx = MI->getOperand(2).getImm();
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assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
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"Extract supperg source must be a physical register");
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unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
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unsigned DstReg = MI->getOperand(0).getReg();
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DOUT << "subreg: CONVERTING: " << *MI;
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if (SrcReg != DstReg) {
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const TargetRegisterClass *TRC = 0;
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if (MRegisterInfo::isPhysicalRegister(DstReg)) {
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TRC = getPhysicalRegisterRegClass(MRI, DstReg);
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} else {
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TRC = MF.getSSARegMap()->getRegClass(DstReg);
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}
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assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
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"Extract subreg and Dst must be of same register class");
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MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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}
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DOUT << "\n";
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MBB->remove(MI);
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return true;
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}
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bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction &MF = *MBB->getParent();
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const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
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unsigned DstReg = 0;
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unsigned SrcReg = 0;
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unsigned InsReg = 0;
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unsigned SubIdx = 0;
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// If only have 3 operands, then the source superreg is undef
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// and we can supress the copy from the undef value
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if (MI->getNumOperands() == 3) {
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assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
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(MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
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MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
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DstReg = MI->getOperand(0).getReg();
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SrcReg = DstReg;
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InsReg = MI->getOperand(1).getReg();
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SubIdx = MI->getOperand(2).getImm();
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} else if (MI->getNumOperands() == 4) {
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assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
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(MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
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(MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
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MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
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DstReg = MI->getOperand(0).getReg();
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SrcReg = MI->getOperand(1).getReg();
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InsReg = MI->getOperand(2).getReg();
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SubIdx = MI->getOperand(3).getImm();
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} else
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assert(0 && "Malformed extract_subreg");
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assert(SubIdx != 0 && "Invalid index for extract_subreg");
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unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
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assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
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"Insert superreg source must be in a physical register");
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assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
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"Insert destination must be in a physical register");
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assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
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"Inserted value must be in a physical register");
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DOUT << "subreg: CONVERTING: " << *MI;
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// If the inserted register is already allocated into a subregister
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// of the destination, we copy the subreg into the source
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// However, this is only safe if the insert instruction is the kill
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// of the source register
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bool revCopyOrder = MRI.isSubRegister(DstReg, InsReg);
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if (revCopyOrder && InsReg != DstSubReg) {
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if (MI->getOperand(1).isKill()) {
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DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
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// Insert sub-register copy
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const TargetRegisterClass *TRC1 = 0;
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if (MRegisterInfo::isPhysicalRegister(InsReg)) {
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TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
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} else {
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TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
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}
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MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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#endif
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} else {
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assert(0 && "Don't know how to convert this insert");
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}
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}
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#ifndef NDEBUG
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if (InsReg == DstSubReg) {
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DOUT << "subreg: Eliminated subreg copy\n";
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}
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#endif
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if (SrcReg != DstReg) {
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// Insert super-register copy
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const TargetRegisterClass *TRC0 = 0;
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if (MRegisterInfo::isPhysicalRegister(DstReg)) {
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TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
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} else {
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TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
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}
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assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
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"Insert superreg and Dst must be of same register class");
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MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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#endif
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}
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#ifndef NDEBUG
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if (SrcReg == DstReg) {
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DOUT << "subreg: Eliminated superreg copy\n";
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}
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#endif
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if (!revCopyOrder && InsReg != DstSubReg) {
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// Insert sub-register copy
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const TargetRegisterClass *TRC1 = 0;
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if (MRegisterInfo::isPhysicalRegister(InsReg)) {
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TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
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} else {
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TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
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}
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MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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#endif
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}
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DOUT << "\n";
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MBB->remove(MI);
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return true;
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}
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/// runOnMachineFunction - Reduce subregister inserts and extracts to register
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/// copies.
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///
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bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DOUT << "Machine Function\n";
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bool MadeChange = false;
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DOUT << "********** LOWERING SUBREG INSTRS **********\n";
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DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
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for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
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mi != me;) {
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MachineInstr *MI = mi++;
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if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
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MadeChange |= LowerExtract(MI);
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} else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
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MadeChange |= LowerInsert(MI);
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}
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}
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}
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return MadeChange;
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}
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