Jakob Stoklund Olesen 89bea17af2 Avoid rewriting instructions twice. ...

This could cause miscompilations in targets where sub-register
composition is not always idempotent (ARM).

<rdar://problem/12758887>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168837 91177308-0d34-0410-b5e6-96231b3b80d8

2012-11-29 00:26:11 +00:00

..

ARM

Avoid rewriting instructions twice.

2012-11-29 00:26:11 +00:00

CPP

test commit

2012-07-18 17:53:05 +00:00

Generic

Codegen support for arbitrary vector getelementptrs.

2012-11-13 13:01:58 +00:00

Hexagon

test/CodeGen/Hexagon/postinc-load.ll: Suppress it for now. It triggered the failure on i686 hosts.

2012-11-14 22:22:37 +00:00

MBlaze

…

Mips

[mips] Generate big GOT code.

2012-11-21 20:40:38 +00:00

MSP430

Add support for varargs functions for msp430.

2012-11-21 17:28:27 +00:00

NVPTX

[NVPTX] Order global variables in def-use order before emiting them in the final assembly

2012-11-16 21:03:51 +00:00

PowerPC

This patch makes medium code model the default for 64-bit PowerPC ELF.

2012-11-27 23:36:26 +00:00

SPARC

Use TargetTransformInfo to control switch-to-lookup table transformation

2012-10-30 11:23:25 +00:00

Thumb

Convert an improper CodeGen test to a MC test.

2012-11-10 04:30:40 +00:00

Thumb2

Add GPRPair Register class to ARM.

2012-10-26 21:29:15 +00:00

X86

When combining consecutive stores allow loads in between the stores, if the loads do not alias.

2012-11-29 00:00:08 +00:00

XCore

Fix handling of aliases to functions.

2012-11-16 21:12:38 +00:00