mirror of
https://github.com/c64scene-ar/llvm-6502.git
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3e883734fa
and allow some optimizations to turn conditional branches into unconditional. This commit adds a simple control-flow optimization which merges two consecutive basic blocks which are connected by a single edge. This allows the codegen to operate on larger basic blocks. rdar://11973998 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161852 91177308-0d34-0410-b5e6-96231b3b80d8
103 lines
3.6 KiB
LLVM
103 lines
3.6 KiB
LLVM
; RUN: llc < %s -O3 -march=thumb -mcpu=cortex-a8 | FileCheck %s
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;
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; LSR should only check for valid address modes when the IV user is a
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; memory address.
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; svn r158536, rdar://11635990
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;
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; Note that we still don't produce the best code here because we fail
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; to coalesce the IV. See <rdar://problem/11680670> [coalescer] IVs
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; need to be scheduled to expose coalescing.
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; LSR before the fix:
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;The chosen solution requires 4 regs, with addrec cost 1, plus 3 base adds, plus 2 setup cost:
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; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
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; reg(%v3) + reg({0,+,-1}<%while.cond.i.i>) + imm(1)
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; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i32
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; reg(%v3) + reg({0,+,-1}<%while.cond.i.i>)
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; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
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; reg((-4 + (4 * %v3) + %v1)) + 4*reg({0,+,-1}<%while.cond.i.i>)
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; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
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; reg((-4 + (4 * %v3) + %v4)) + 4*reg({0,+,-1}<%while.cond.i.i>)
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; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
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; reg(%v3)
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;
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; LSR after the fix:
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;The chosen solution requires 4 regs, with addrec cost 1, plus 1 base add, plus 2 setup cost:
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; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
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; reg({%v3,+,-1}<nsw><%while.cond.i.i>) + imm(1)
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; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i32
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; reg({%v3,+,-1}<nsw><%while.cond.i.i>)
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; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
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; reg((-4 + %v1)) + 4*reg({%v3,+,-1}<nsw><%while.cond.i.i>)
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; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
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; reg((-4 + %v4)) + 4*reg({%v3,+,-1}<nsw><%while.cond.i.i>)
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; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
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; reg(%v3)
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%s = type { i32* }
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@ncol = external global i32, align 4
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declare i32* @getptr() nounwind
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declare %s* @getstruct() nounwind
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; CHECK: @main
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; Check that the loop preheader contains no address computation.
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; CHECK: %end_of_chain
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; CHECK-NOT: add{{.*}}lsl
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; CHECK: ldr{{.*}}lsl #2
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; CHECK: ldr{{.*}}lsl #2
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define i32 @main() nounwind ssp {
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entry:
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%v0 = load i32* @ncol, align 4, !tbaa !0
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%v1 = tail call i32* @getptr() nounwind
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%cmp10.i = icmp eq i32 %v0, 0
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br label %while.cond.outer
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while.cond.outer:
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%call18 = tail call %s* @getstruct() nounwind
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br label %while.cond
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while.cond:
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%cmp20 = icmp eq i32* %v1, null
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br label %while.body
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while.body:
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%v3 = load i32* @ncol, align 4, !tbaa !0
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br label %end_of_chain
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end_of_chain:
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%state.i = getelementptr inbounds %s* %call18, i32 0, i32 0
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%v4 = load i32** %state.i, align 4, !tbaa !3
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br label %while.cond.i.i
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while.cond.i.i:
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%counter.0.i.i = phi i32 [ %v3, %end_of_chain ], [ %dec.i.i, %land.rhs.i.i ]
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%dec.i.i = add nsw i32 %counter.0.i.i, -1
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%tobool.i.i = icmp eq i32 %counter.0.i.i, 0
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br i1 %tobool.i.i, label %where.exit, label %land.rhs.i.i
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land.rhs.i.i:
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%arrayidx.i.i = getelementptr inbounds i32* %v4, i32 %dec.i.i
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%v5 = load i32* %arrayidx.i.i, align 4, !tbaa !0
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%arrayidx1.i.i = getelementptr inbounds i32* %v1, i32 %dec.i.i
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%v6 = load i32* %arrayidx1.i.i, align 4, !tbaa !0
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%cmp.i.i = icmp eq i32 %v5, %v6
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br i1 %cmp.i.i, label %while.cond.i.i, label %equal_data.exit.i
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equal_data.exit.i:
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ret i32 %counter.0.i.i
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where.exit:
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br label %while.end.i
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while.end.i:
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ret i32 %v3
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}
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!0 = metadata !{metadata !"int", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA"}
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!3 = metadata !{metadata !"any pointer", metadata !1}
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