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https://github.com/c64scene-ar/llvm-6502.git
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a499d2bcef
Something very strange is going on with the output registers in this target. Its ISelLowering code is inserting dangling CopyToReg nodes, hoping that those physregs won't get clobbered before the RETURN. This patch adds the output registers as implicit uses on RETURN instructions in the custom emission pass. I'd much prefer to have those CopyToReg nodes glued to the RETURNs, but I don't see how. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174400 91177308-0d34-0410-b5e6-96231b3b80d8
33 lines
871 B
C++
33 lines
871 B
C++
//===-- R600MachineFunctionInfo.h - R600 Machine Function Info ----*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef R600MACHINEFUNCTIONINFO_H
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#define R600MACHINEFUNCTIONINFO_H
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include <vector>
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namespace llvm {
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class R600MachineFunctionInfo : public MachineFunctionInfo {
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public:
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R600MachineFunctionInfo(const MachineFunction &MF);
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SmallVector<unsigned, 4> LiveOuts;
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SDNode *Outputs[16];
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};
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} // End llvm namespace
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#endif //R600MACHINEFUNCTIONINFO_H
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