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a74341308f
This WebAssembly backend is just a skeleton at this time and is not yet functional. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241022 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
2.2 KiB
TableGen
59 lines
2.2 KiB
TableGen
//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the WebAssembly architecture, which is
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// also known as "wasm".
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// WebAssembly Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureSIMD : SubtargetFeature<"simd", "HasSIMD", "true",
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"Enable SIMD">;
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//===----------------------------------------------------------------------===//
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// Architectures.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "WebAssemblyRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrInfo.td"
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def WebAssemblyInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// WebAssembly Processors supported.
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//===----------------------------------------------------------------------===//
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def : ProcessorModel<"generic", NoSchedModel, [FeatureSIMD]>;
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//===----------------------------------------------------------------------===//
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// Target Declaration
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//===----------------------------------------------------------------------===//
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def WebAssembly : Target {
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let InstructionSet = WebAssemblyInstrInfo;
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}
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