Benjamin Kramer d25ec760cb X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equivalent. ...

Give it the right register format so we can also emit it when AVX is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183971 91177308-0d34-0410-b5e6-96231b3b80d8

2013-06-14 09:31:41 +00:00

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AArch64

Change how we iterate over relocations on ELF.

2013-05-30 03:05:14 +00:00

ARM

Enable FastISel on ARM for Linux and NaCl, not MCJIT

2013-06-14 02:49:43 +00:00

CPP

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Generic

Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.

2013-05-21 14:37:16 +00:00

Hexagon

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Inputs

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MBlaze

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Mips

[mips] Add an IR transformation pass that optimizes calls to sqrt.

2013-06-11 22:21:44 +00:00

MSP430

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NVPTX

[NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space

2013-06-10 13:29:47 +00:00

PowerPC

[PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.

2013-06-13 20:23:34 +00:00

R600

R600: Anti dep better handled in tex clause

2013-06-07 23:30:26 +00:00

SI

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SPARC

[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.

2013-06-08 15:32:59 +00:00

SystemZ

[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses

2013-05-31 13:25:22 +00:00

Thumb

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Thumb2

Cortex-R5 can issue Thumb2 integer division instructions.

2013-06-04 22:52:09 +00:00

X86

X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equivalent.

2013-06-14 09:31:41 +00:00

XCore

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