Richard Osborne 850f1cd3c0 Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit ...

expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98168 91177308-0d34-0410-b5e6-96231b3b80d8

2010-03-10 18:12:27 +00:00

..

Alpha

Fix PR2590 by making PatternSortingPredicate actually be

2010-03-01 22:09:11 +00:00

ARM

Enable machine cse pass.

2010-03-10 03:07:41 +00:00

Blackfin

Change the scheduler from adding nodes in allnodes order

2010-02-24 06:11:37 +00:00

CBackend

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CellSPU

fix bss section printing for cell, patch by Kalle Raiskila!

2010-03-05 18:55:36 +00:00

CPP

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Generic

stop using anders-aa

2010-03-01 20:24:05 +00:00

MBlaze

Re-committing the failed r97807 commit with changes to eliminate warnings.

2010-03-06 23:23:12 +00:00

Mips

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MSP430

Do not use '&' prefix for globals when register base field is non-zero, otherwise msp430-as will silently miscompile the code (TI's assembler report an error though).

2010-03-06 11:41:12 +00:00

PIC16

this testcase is failing because pic16 doesn't define a reg/reg

2010-03-02 20:48:24 +00:00

PowerPC

Enable machine cse pass.

2010-03-10 03:07:41 +00:00

SPARC

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SystemZ

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Thumb

Enable machine cse pass.

2010-03-10 03:07:41 +00:00

Thumb2

Enable machine cse pass.

2010-03-10 03:07:41 +00:00

X86

Fix typo.

2010-03-10 07:07:55 +00:00

XCore

Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit

2010-03-10 18:12:27 +00:00