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0e1158f340
Currently schedules one basic block at a time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@396 91177308-0d34-0410-b5e6-96231b3b80d8
87 lines
2.6 KiB
C++
87 lines
2.6 KiB
C++
// $Id$
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//***************************************************************************
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// File:
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// InstrScheduling.h
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//
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// Purpose:
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//
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// History:
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// 7/23/01 - Vikram Adve - Created
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//***************************************************************************
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#ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
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#define LLVM_CODEGEN_INSTR_SCHEDULING_H
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//************************ User Include Files *****************************/
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#include "llvm/Support/CommandLine.h"
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#include "llvm/CodeGen/TargetMachine.h"
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//************************ Opaque Declarations*****************************/
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class Method;
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class SchedulingManager;
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//************************ Exported Data Types *****************************/
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// Debug option levels for instruction scheduling
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enum SchedDebugLevel_t {
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Sched_NoDebugInfo,
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Sched_PrintMachineCode,
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Sched_PrintSchedTrace,
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Sched_PrintSchedGraphs,
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};
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extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
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//************************** External Classes ******************************/
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//************************* External Functions *****************************/
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//---------------------------------------------------------------------------
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// Function: ScheduleInstructionsWithSSA
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//
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// Purpose:
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// Entry point for instruction scheduling on SSA form.
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// Schedules the machine instructions generated by instruction selection.
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// Assumes that register allocation has not been done, i.e., operands
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// are still in SSA form.
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//---------------------------------------------------------------------------
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bool ScheduleInstructionsWithSSA (Method* method,
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const TargetMachine &Target);
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//---------------------------------------------------------------------------
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// Function: ScheduleInstructions
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//
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// Purpose:
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// Entry point for instruction scheduling on machine code.
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// Schedules the machine instructions generated by instruction selection.
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// Assumes that register allocation has been done.
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//---------------------------------------------------------------------------
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// Not implemented yet.
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bool ScheduleInstructions (Method* method,
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const TargetMachine &Target);
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//---------------------------------------------------------------------------
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// Function: instrIsFeasible
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//
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// Purpose:
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// Used by the priority analysis to filter out instructions
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// that are not feasible to issue in the current cycle.
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// Should only be used during schedule construction..
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//---------------------------------------------------------------------------
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bool instrIsFeasible (const SchedulingManager& S,
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MachineOpCode opCode);
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//**************************************************************************/
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#endif
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