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d6a77822a9
callee-saved scan. The code makes use of register's scavenger's capability to spill multiple registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178391 91177308-0d34-0410-b5e6-96231b3b80d8
469 lines
17 KiB
C++
469 lines
17 KiB
C++
//===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips32/64 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEFrameLowering.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsMachineFunction.h"
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#include "MipsSEInstrInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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namespace {
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typedef MachineBasicBlock::iterator Iter;
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/// Helper class to expand accumulator pseudos.
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class ExpandACCPseudo {
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public:
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ExpandACCPseudo(MachineFunction &MF);
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bool expand();
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private:
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bool expandInstr(MachineBasicBlock &MBB, Iter I);
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void expandLoad(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
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void expandStore(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
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void expandCopy(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
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MachineFunction &MF;
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const MipsSEInstrInfo &TII;
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const MipsRegisterInfo &RegInfo;
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MachineRegisterInfo &MRI;
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};
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}
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ExpandACCPseudo::ExpandACCPseudo(MachineFunction &MF_)
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: MF(MF_),
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TII(*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo())),
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RegInfo(TII.getRegisterInfo()), MRI(MF.getRegInfo()) {}
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bool ExpandACCPseudo::expand() {
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bool Expanded = false;
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for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
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BB != BBEnd; ++BB)
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for (Iter I = BB->begin(), End = BB->end(); I != End;)
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Expanded |= expandInstr(*BB, I++);
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return Expanded;
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}
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bool ExpandACCPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
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switch(I->getOpcode()) {
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case Mips::LOAD_AC64:
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case Mips::LOAD_AC64_P8:
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case Mips::LOAD_AC_DSP:
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case Mips::LOAD_AC_DSP_P8:
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expandLoad(MBB, I, 4);
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break;
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case Mips::LOAD_AC128:
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case Mips::LOAD_AC128_P8:
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expandLoad(MBB, I, 8);
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break;
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case Mips::STORE_AC64:
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case Mips::STORE_AC64_P8:
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case Mips::STORE_AC_DSP:
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case Mips::STORE_AC_DSP_P8:
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expandStore(MBB, I, 4);
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break;
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case Mips::STORE_AC128:
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case Mips::STORE_AC128_P8:
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expandStore(MBB, I, 8);
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break;
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case Mips::COPY_AC64:
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case Mips::COPY_AC_DSP:
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expandCopy(MBB, I, 4);
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break;
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case Mips::COPY_AC128:
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expandCopy(MBB, I, 8);
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break;
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default:
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return false;
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}
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MBB.erase(I);
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return true;
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}
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void ExpandACCPseudo::expandLoad(MachineBasicBlock &MBB, Iter I,
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unsigned RegSize) {
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// load $vr0, FI
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// copy lo, $vr0
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// load $vr1, FI + 4
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// copy hi, $vr1
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
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unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
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DebugLoc DL = I->getDebugLoc();
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const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
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TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
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BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
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TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
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BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
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}
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void ExpandACCPseudo::expandStore(MachineBasicBlock &MBB, Iter I,
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unsigned RegSize) {
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// copy $vr0, lo
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// store $vr0, FI
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// copy $vr1, hi
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// store $vr1, FI + 4
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assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
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unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
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unsigned Lo = RegInfo.getSubReg(Src, Mips::sub_lo);
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unsigned Hi = RegInfo.getSubReg(Src, Mips::sub_hi);
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DebugLoc DL = I->getDebugLoc();
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BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(Lo, SrcKill);
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TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
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BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(Hi, SrcKill);
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TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
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}
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void ExpandACCPseudo::expandCopy(MachineBasicBlock &MBB, Iter I,
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unsigned RegSize) {
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// copy $vr0, src_lo
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// copy dst_lo, $vr0
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// copy $vr1, src_hi
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// copy dst_hi, $vr1
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const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
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unsigned VR0 = MRI.createVirtualRegister(RC);
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unsigned VR1 = MRI.createVirtualRegister(RC);
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unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
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unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
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unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
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unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
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unsigned SrcLo = RegInfo.getSubReg(Src, Mips::sub_lo);
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unsigned SrcHi = RegInfo.getSubReg(Src, Mips::sub_hi);
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DebugLoc DL = I->getDebugLoc();
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BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(SrcLo, SrcKill);
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BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
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.addReg(VR0, RegState::Kill);
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BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(SrcHi, SrcKill);
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BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
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.addReg(VR1, RegState::Kill);
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}
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unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const {
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static const unsigned EhDataReg[] = {
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Mips::A0, Mips::A1, Mips::A2, Mips::A3
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};
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static const unsigned EhDataReg64[] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
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};
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return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
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}
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void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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// First, compute final stack size.
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uint64_t StackSize = MFI->getStackSize();
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->adjustsStack()) return;
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MachineModuleInfo &MMI = MF.getMMI();
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std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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MachineLocation DstML, SrcML;
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// Adjust stack.
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TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
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// emit ".cfi_def_cfa_offset StackSize"
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MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
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DstML = MachineLocation(MachineLocation::VirtualFP);
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SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
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Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.size()) {
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// Find the instruction past the last instruction that saves a callee-saved
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// register to the stack.
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for (unsigned i = 0; i < CSI.size(); ++i)
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++MBBI;
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// Iterate over list of callee-saved registers and emit .cfi_offset
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// directives.
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MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
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unsigned Reg = I->getReg();
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// If Reg is a double precision register, emit two cfa_offsets,
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// one for each of the paired single precision registers.
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if (Mips::AFGR64RegClass.contains(Reg)) {
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MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
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MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
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MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
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MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
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if (!STI.isLittle())
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std::swap(SrcML0, SrcML1);
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Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
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Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
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} else {
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// Reg is either in CPURegs or FGR32.
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DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
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SrcML = MachineLocation(Reg);
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Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
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}
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}
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}
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if (MipsFI->callsEhReturn()) {
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const TargetRegisterClass *RC = STI.isABI_N64() ?
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&Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
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// Insert instructions that spill eh data registers.
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for (int I = 0; I < 4; ++I) {
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if (!MBB.isLiveIn(ehDataReg(I)))
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MBB.addLiveIn(ehDataReg(I));
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TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
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MipsFI->getEhDataRegFI(I), RC, RegInfo);
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}
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// Emit .cfi_offset directives for eh data registers.
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MCSymbol *CSLabel2 = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
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for (int I = 0; I < 4; ++I) {
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int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
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DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
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SrcML = MachineLocation(ehDataReg(I));
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Moves.push_back(MachineMove(CSLabel2, DstML, SrcML));
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}
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}
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// if framepointer enabled, set it to point to the stack pointer.
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if (hasFP(MF)) {
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// Insert instruction "move $fp, $sp" at this location.
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BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
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// emit ".cfi_def_cfa_register $fp"
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MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
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DstML = MachineLocation(FP);
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SrcML = MachineLocation(MachineLocation::VirtualFP);
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Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
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}
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}
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void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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// if framepointer enabled, restore the stack pointer.
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if (hasFP(MF)) {
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// Find the first instruction that restores a callee-saved register.
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MachineBasicBlock::iterator I = MBBI;
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for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
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--I;
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// Insert instruction "move $sp, $fp" at this location.
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BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
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}
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if (MipsFI->callsEhReturn()) {
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const TargetRegisterClass *RC = STI.isABI_N64() ?
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&Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
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// Find first instruction that restores a callee-saved register.
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MachineBasicBlock::iterator I = MBBI;
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for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
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--I;
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// Insert instructions that restore eh data registers.
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for (int J = 0; J < 4; ++J) {
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TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
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RC, RegInfo);
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}
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}
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// Get the number of bytes from FrameInfo
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uint64_t StackSize = MFI->getStackSize();
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if (!StackSize)
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return;
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// Adjust stack.
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TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
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}
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bool MipsSEFrameLowering::
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spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineFunction *MF = MBB.getParent();
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MachineBasicBlock *EntryBlock = MF->begin();
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const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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// Add the callee-saved register as live-in. Do not add if the register is
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// RA and return address is taken, because it has already been added in
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// method MipsTargetLowering::LowerRETURNADDR.
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// It's killed at the spill, unless the register is RA and return address
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// is taken.
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unsigned Reg = CSI[i].getReg();
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bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
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&& MF->getFrameInfo()->isReturnAddressTaken();
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if (!IsRAAndRetAddrIsTaken)
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EntryBlock->addLiveIn(Reg);
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// Insert the spill to the stack frame.
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bool IsKill = !IsRAAndRetAddrIsTaken;
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
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CSI[i].getFrameIdx(), RC, TRI);
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}
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return true;
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}
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bool
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MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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// Reserve call frame if the size of the maximum call frame fits into 16-bit
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// immediate field and there are no variable sized objects on the stack.
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// Make sure the second register scavenger spill slot can be accessed with one
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// instruction.
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return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) &&
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!MFI->hasVarSizedObjects();
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}
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// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
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void MipsSEFrameLowering::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const MipsSEInstrInfo &TII =
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*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
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if (!hasReservedCallFrame(MF)) {
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int64_t Amount = I->getOperand(0).getImm();
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if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
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Amount = -Amount;
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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TII.adjustStackPtr(SP, Amount, MBB, I);
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}
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MBB.erase(I);
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}
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void MipsSEFrameLowering::
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processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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// Mark $fp as used if function has dedicated frame pointer.
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if (hasFP(MF))
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MRI.setPhysRegUsed(FP);
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// Create spill slots for eh data registers if function calls eh_return.
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if (MipsFI->callsEhReturn())
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MipsFI->createEhDataRegsFI();
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// Expand pseudo instructions which load, store or copy accumulators.
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// Add an emergency spill slot if a pseudo was expanded.
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if (ExpandACCPseudo(MF).expand()) {
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// The spill slot should be half the size of the accumulator. If target is
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// mips64, it should be 64-bit, otherwise it should be 32-bt.
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const TargetRegisterClass *RC = STI.hasMips64() ?
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&Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
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int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment(), false);
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RS->addScavengingFrameIndex(FI);
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}
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|
|
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// Set scavenging frame index if necessary.
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uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
|
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estimateStackSize(MF);
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|
|
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if (isInt<16>(MaxSPOffset))
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return;
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|
|
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const TargetRegisterClass *RC = STI.isABI_N64() ?
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&Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
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int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment(), false);
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RS->addScavengingFrameIndex(FI);
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}
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|
|
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const MipsFrameLowering *
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llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
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return new MipsSEFrameLowering(ST);
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|
}
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