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llvm-6502/test/CodeGen/AArch64
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Juergen Ributzka af989653e0 [FastISel][AArch64] Also allow folding of sign-/zero-extend and shift-left for booleans (i1). 
Shift-left immediate with sign-/zero-extensions also works for boolean values.
Update the assert and the test cases to reflect that fact.

This should fix a bug found by Chad.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218275 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-22 21:08:53 +00:00
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128bit_load_store.ll
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a57-csel.ll
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aarch64_f16_be.ll
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aarch64_tree_tests.ll
Build correct vector filled with undef nodes
2014-09-11 05:10:28 +00:00
aarch64-2014-08-11-MachineCombinerCrash.ll
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aarch64-a57-fp-load-balancing.ll
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aarch64-address-type-promotion-assertion.ll
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aarch64-address-type-promotion.ll
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aarch64-be-bv.ll
AArch64: fix vector-immediate BIC/ORR on big-endian devices.
2014-09-04 15:05:24 +00:00
aarch64-neon-v1i1-setcc.ll
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adc.ll
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addsub_ext.ll
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addsub-shifted.ll
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addsub.ll
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alloca.ll
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analyze-branch.ll
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analyzecmp.ll
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and-mask-removal.ll
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andandshift.ll
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arm64-2011-03-09-CPSRSpill.ll
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arm64-2011-03-17-AsmPrinterCrash.ll
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arm64-2011-03-21-Unaligned-Frame-Index.ll
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arm64-2011-04-21-CPSRBug.ll
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arm64-2011-10-18-LdStOptBug.ll
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arm64-2012-01-11-ComparisonDAGCrash.ll
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arm64-2012-05-07-DAGCombineVectorExtract.ll
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arm64-2012-05-07-MemcpyAlignBug.ll
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arm64-2012-05-09-LOADgot-bug.ll
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arm64-2012-05-22-LdStOptBug.ll
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arm64-2012-06-06-FPToUI.ll
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arm64-2012-07-11-InstrEmitterBug.ll
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arm64-2013-01-13-ffast-fcmp.ll
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arm64-2013-01-23-frem-crash.ll
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arm64-2013-01-23-sext-crash.ll
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arm64-2013-02-12-shufv8i8.ll
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arm64-aapcs-be.ll
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arm64-aapcs.ll
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arm64-abi_align.ll
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arm64-abi-varargs.ll
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arm64-abi.ll
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arm64-addp.ll
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arm64-addr-mode-folding.ll
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arm64-addr-type-promotion.ll
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arm64-addrmode.ll
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arm64-AdvSIMD-Scalar.ll
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arm64-alloc-no-stack-realign.ll
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arm64-alloca-frame-pointer-offset.ll
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arm64-andCmpBrToTBZ.ll
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arm64-ands-bad-peephole.ll
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arm64-AnInfiniteLoopInDAGCombine.ll
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arm64-anyregcc-crash.ll
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arm64-anyregcc.ll
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arm64-arith-saturating.ll
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arm64-arith.ll
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arm64-arm64-dead-def-elimination-flag.ll
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arm64-atomic-128.ll
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arm64-atomic.ll
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arm64-basic-pic.ll
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arm64-big-endian-bitconverts.ll
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arm64-big-endian-eh.ll
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arm64-big-endian-varargs.ll
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arm64-big-endian-vector-callee.ll
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arm64-big-endian-vector-caller.ll
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arm64-big-imm-offsets.ll
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arm64-big-stack.ll
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arm64-bitfield-extract.ll
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arm64-blockaddress.ll
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arm64-build-vector.ll
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arm64-call-tailcalls.ll
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arm64-cast-opt.ll
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arm64-ccmp-heuristics.ll
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arm64-ccmp.ll
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arm64-clrsb.ll
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arm64-coalesce-ext.ll
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arm64-code-model-large-abs.ll
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arm64-collect-loh-garbage-crash.ll
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arm64-collect-loh-str.ll
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arm64-collect-loh.ll
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arm64-complex-copy-noneon.ll
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arm64-complex-ret.ll
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arm64-const-addr.ll
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arm64-convert-v4f64.ll
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arm64-copy-tuple.ll
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arm64-crc32.ll
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arm64-crypto.ll
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arm64-cse.ll
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arm64-csel.ll
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arm64-cvt.ll
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arm64-dagcombiner-convergence.ll
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arm64-dagcombiner-dead-indexed-load.ll
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arm64-dagcombiner-load-slicing.ll
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arm64-dead-def-frame-index.ll
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arm64-dead-register-def-bug.ll
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arm64-dup.ll
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arm64-early-ifcvt.ll
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arm64-elf-calls.ll
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arm64-elf-constpool.ll
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arm64-elf-globals.ll
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arm64-EXT-undef-mask.ll
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arm64-ext.ll
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arm64-extend-int-to-fp.ll
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arm64-extend.ll
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arm64-extern-weak.ll
[AArch 64] Use a constant pool load for weak symbol references when
2014-09-10 13:54:38 +00:00
arm64-extload-knownzero.ll
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arm64-extract_subvector.ll
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arm64-extract.ll
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arm64-fast-isel-addr-offset.ll
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arm64-fast-isel-alloca.ll
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arm64-fast-isel-br.ll
[FastISel][AArch64] Add target-specific lowering for logical operations.
2014-09-04 01:29:18 +00:00
arm64-fast-isel-call.ll
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arm64-fast-isel-conversion.ll
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arm64-fast-isel-fcmp.ll
[FastISel][AArch64] Improve floating-point compare support.
2014-09-15 20:47:16 +00:00
arm64-fast-isel-gv.ll
[FastISel][AArch64] Add target-specific lowering for logical operations.
2014-09-04 01:29:18 +00:00
arm64-fast-isel-icmp.ll
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arm64-fast-isel-indirectbr.ll
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arm64-fast-isel-intrinsic.ll
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arm64-fast-isel-materialize.ll
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arm64-fast-isel-noconvert.ll
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arm64-fast-isel-rem.ll
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arm64-fast-isel-ret.ll
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arm64-fast-isel-select.ll
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arm64-fast-isel-store.ll
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arm64-fast-isel.ll
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arm64-fastcc-tailcall.ll
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arm64-fastisel-gep-promote-before-add.ll
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arm64-fcmp-opt.ll
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arm64-fcopysign.ll
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arm64-fixed-point-scalar-cvt-dagcombine.ll
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arm64-fmadd.ll
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arm64-fmax.ll
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arm64-fminv.ll
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arm64-fmuladd.ll
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arm64-fold-address.ll
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arm64-fold-lsl.ll
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arm64-fp128-folding.ll
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arm64-fp128.ll
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arm64-fp-contract-zero.ll
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arm64-fp-imm.ll
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arm64-fp.ll
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arm64-frame-index.ll
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arm64-global-address.ll
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arm64-hello.ll
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arm64-i16-subreg-extract.ll
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arm64-icmp-opt.ll
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arm64-illegal-float-ops.ll
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arm64-indexed-memory.ll
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arm64-indexed-vector-ldst-2.ll
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arm64-indexed-vector-ldst.ll
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arm64-inline-asm-error-I.ll
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arm64-inline-asm-error-J.ll
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arm64-inline-asm-error-K.ll
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arm64-inline-asm-error-L.ll
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arm64-inline-asm-error-M.ll
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arm64-inline-asm-error-N.ll
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arm64-inline-asm-zero-reg-error.ll
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arm64-inline-asm.ll
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arm64-join-reserved.ll
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arm64-jumptable.ll
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arm64-large-frame.ll
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arm64-ld1.ll
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arm64-ldp.ll
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arm64-ldur.ll
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arm64-ldxr-stxr.ll
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arm64-leaf.ll
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arm64-long-shift.ll
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arm64-memcpy-inline.ll
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arm64-memset-inline.ll
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arm64-memset-to-bzero.ll
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arm64-misched-basic-A53.ll
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arm64-misched-basic-A57.ll
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arm64-misched-forwarding-A53.ll
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arm64-movi.ll
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arm64-mul.ll
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arm64-named-reg-alloc.ll
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arm64-named-reg-notareg.ll
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arm64-neg.ll
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arm64-neon-2velem-high.ll
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arm64-neon-2velem.ll
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arm64-neon-3vdiff.ll
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arm64-neon-aba-abd.ll
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arm64-neon-across.ll
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arm64-neon-add-pairwise.ll
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arm64-neon-add-sub.ll
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arm64-neon-compare-instructions.ll
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arm64-neon-copy.ll
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arm64-neon-copyPhysReg-tuple.ll
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arm64-neon-mul-div.ll
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arm64-neon-scalar-by-elem-mul.ll
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arm64-neon-select_cc.ll
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arm64-neon-simd-ldst-one.ll
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arm64-neon-simd-shift.ll
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arm64-neon-simd-vget.ll
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arm64-neon-v1i1-setcc.ll
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arm64-neon-vector-list-spill.ll
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arm64-patchpoint-scratch-regs.ll
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arm64-patchpoint-webkit_jscc.ll
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arm64-patchpoint.ll
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arm64-pic-local-symbol.ll
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arm64-platform-reg.ll
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arm64-popcnt.ll
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arm64-prefetch.ll
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arm64-promote-const.ll
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arm64-redzone.ll
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arm64-reg-copy-noneon.ll
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arm64-register-offset-addressing.ll
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arm64-register-pairing.ll
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arm64-regress-f128csel-flags.ll
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arm64-regress-interphase-shift.ll
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arm64-return-vector.ll
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arm64-returnaddr.ll
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arm64-rev.ll
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arm64-rounding.ll
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arm64-scaled_iv.ll
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arm64-scvt.ll
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arm64-setcc-int-to-fp-combine.ll
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arm64-shifted-sext.ll
Add DAG combine for shl + add of constants.
2014-09-11 17:34:19 +00:00
arm64-shrink-v1i64.ll
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arm64-simd-scalar-to-vector.ll
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arm64-simplest-elf.ll
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arm64-sincos.ll
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arm64-sitofp-combine-chains.ll
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arm64-sli-sri-opt.ll
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arm64-smaxv.ll
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arm64-sminv.ll
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arm64-spill-lr.ll
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arm64-spill.ll
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arm64-sqshl-uqshl-i64Contant.ll
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arm64-st1.ll
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arm64-stack-no-frame.ll
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arm64-stackmap.ll
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arm64-stackpointer.ll
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arm64-stacksave.ll
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arm64-stp.ll
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arm64-strict-align.ll
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arm64-stur.ll
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arm64-subsections.ll
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arm64-subvector-extend.ll
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arm64-swizzle-tbl-i16-layout.ll
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arm64-tbl.ll
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arm64-this-return.ll
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arm64-tls-darwin.ll
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arm64-tls-dynamic-together.ll
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arm64-tls-dynamics.ll
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arm64-tls-execs.ll
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arm64-trap.ll
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arm64-triv-disjoint-mem-access.ll
[AArch64] Improve AA to remove unneeded edges in the AA MI scheduling graph.
2014-09-08 14:43:48 +00:00
arm64-trn.ll
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arm64-trunc-store.ll
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arm64-umaxv.ll
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arm64-uminv.ll
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arm64-umov.ll
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arm64-unaligned_ldst.ll
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arm64-uzp.ll
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arm64-vaargs.ll
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arm64-vabs.ll
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arm64-vadd.ll
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arm64-vaddlv.ll
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arm64-vaddv.ll
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arm64-variadic-aapcs.ll
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arm64-vbitwise.ll
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arm64-vclz.ll
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arm64-vcmp.ll
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arm64-vcnt.ll
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arm64-vcombine.ll
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arm64-vcvt_f32_su32.ll
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arm64-vcvt_f.ll
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arm64-vcvt_n.ll
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arm64-vcvt_su32_f32.ll
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arm64-vcvt.ll
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arm64-vcvtxd_f32_f64.ll
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arm64-vecCmpBr.ll
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arm64-vecFold.ll
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arm64-vector-ext.ll
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arm64-vector-imm.ll
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arm64-vector-insertion.ll
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arm64-vector-ldst.ll
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arm64-vext_reverse.ll
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arm64-vext.ll
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arm64-vfloatintrinsics.ll
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arm64-vhadd.ll
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arm64-vhsub.ll
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arm64-virtual_base.ll
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arm64-vmax.ll
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arm64-vminmaxnm.ll
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arm64-vmovn.ll
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arm64-vmul.ll
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arm64-volatile.ll
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arm64-vpopcnt.ll
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arm64-vqadd.ll
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arm64-vqsub.ll
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arm64-vselect.ll
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arm64-vsetcc_fp.ll
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arm64-vshift.ll
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arm64-vshr.ll
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arm64-vshuffle.ll
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arm64-vsqrt.ll
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arm64-vsra.ll
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arm64-vsub.ll
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arm64-weak-reference.ll
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arm64-xaluo.ll
Fix previous commit: [FastISel][AArch64] Simplify XALU multiplies.
2014-09-18 07:26:26 +00:00
arm64-zero-cycle-regmov.ll
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arm64-zero-cycle-zeroing.ll
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arm64-zext.ll
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arm64-zextload-unscaled.ll
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arm64-zip.ll
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asm-large-immediate.ll
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assertion-rc-mismatch.ll
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atomic-ops-not-barriers.ll
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atomic-ops.ll
Optimize sext/zext insertion algorithm in back-end.
2014-09-19 05:30:35 +00:00
basic-pic.ll
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bitfield-insert-0.ll
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bitfield-insert.ll
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bitfield.ll
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blockaddress.ll
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bool-loads.ll
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branch-relax-asm.ll
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breg.ll
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callee-save.ll
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cmpwithshort.ll
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cmpxchg-idioms.ll
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code-model-large-abs.ll
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combine-comparisons-by-cse.ll
[AArch64] Add pass to enable additional comparison optimizations by CSE.
2014-09-05 02:55:24 +00:00
compare-branch.ll
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compiler-ident.ll
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complex-copy-noneon.ll
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complex-fp-to-int.ll
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complex-int-to-fp.ll
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cond-sel.ll
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cpus.ll
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directcond.ll
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dont-take-over-the-world.ll
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dp1.ll
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dp2.ll
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dp-3source.ll
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eliminate-trunc.ll
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extern-weak.ll
[AArch 64] Use a constant pool load for weak symbol references when
2014-09-10 13:54:38 +00:00
extract.ll
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f16-convert.ll
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fast-isel-addressing-modes.ll
[FastIsel][AArch64] Fix a think-o in address computation.
2014-09-19 22:23:46 +00:00
fast-isel-branch_weights.ll
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fast-isel-call-return.ll
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fast-isel-cbz.ll
[FastISel][AArch64] Fold compare with zero and branch into CBZ and CBNZ.
2014-09-17 18:05:34 +00:00
fast-isel-cmp-branch.ll
[FastISel][AArch64] Improve branch selection to support all FP conditions.
2014-09-17 17:46:47 +00:00
fast-isel-folding.ll
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fast-isel-logic-op.ll
[FastISel][AArch64] Fold mul into add/sub and logical operations.
2014-09-17 19:51:38 +00:00
fast-isel-mul.ll
[FastISel][AArch64] Simplify mul to shift when possible.
2014-09-17 20:35:41 +00:00
fast-isel-runtime-libcall.ll
[FastISel][AArch64] Lower sin/cos/pow to runtime lib calls.
2014-09-15 22:33:06 +00:00
fast-isel-sdiv.ll
[FastISel][AArch64] Custom lower sdiv by power-of-2.
2014-09-17 21:55:55 +00:00
fast-isel-shift.ll
[FastISel][AArch64] Also allow folding of sign-/zero-extend and shift-left for booleans (i1).
2014-09-22 21:08:53 +00:00
fast-isel-sqrt.ll
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fast-isel-switch-phi.ll
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fast-isel-trunc.ll
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fast-isel-vector-arithmetic.ll
[FastISel][AArch64] Add vector support to argument lowering.
2014-09-16 00:25:30 +00:00
fast-isel-vret.ll
[FastISel][AArch64] Add missing test case for previous commit.
2014-09-15 23:47:57 +00:00
fastcc-reserved.ll
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fastcc.ll
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fcmp.ll
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fcvt-fixed.ll
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fcvt-int.ll
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flags-multiuse.ll
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floatdp_1source.ll
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floatdp_2source.ll
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fp16-instructions.ll
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fp16-v4-instructions.ll
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fp16-v8-instructions.ll
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fp16-vector-bitcast.ll
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fp16-vector-load-store.ll
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fp16-vector-shuffle.ll
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fp128-folding.ll
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fp-cond-sel.ll
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fp-dp3.ll
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fpimm.ll
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frameaddr.ll
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free-zext.ll
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func-argpassing.ll
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func-calls.ll
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funcptr_cast.ll
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global-alignment.ll
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global-merge-1.ll
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global-merge-2.ll
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global-merge-3.ll
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global-merge-4.ll
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global-merge.ll
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got-abuse.ll
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half.ll
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hints.ll
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i1-contents.ll
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i128-align.ll
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i128-fast-isel-fallback.ll
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illegal-float-ops.ll
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init-array.ll
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inline-asm-constraints-badI.ll
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inline-asm-constraints-badK2.ll
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inline-asm-constraints-badK.ll
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inline-asm-constraints-badL.ll
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inlineasm-ldr-pseudo.ll
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intrinsics-memory-barrier.ll
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jump-table.ll
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large-consts.ll
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ldst-opt.ll
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ldst-regoffset.ll
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ldst-unscaledimm.ll
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ldst-unsignedimm.ll
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lit.local.cfg
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literal_pools_float.ll
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local_vars.ll
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logical_shifted_reg.ll
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logical-imm.ll
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machine_cse.ll
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madd-combiner.ll
Reapply r216805 "[MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR.""
2014-09-03 07:07:10 +00:00
madd-lohi.ll
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mature-mc-support.ll
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memcpy-f128.ll
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movw-consts.ll
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movw-shift-encoding.ll
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mul_pow2.ll
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mul-lohi.ll
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neon-bitcast.ll
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neon-bitwise-instructions.ll
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neon-compare-instructions.ll
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neon-diagnostics.ll
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neon-extract.ll
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neon-fma.ll
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neon-fpround_f128.ll
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neon-idiv.ll
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neon-mla-mls.ll
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neon-mov.ll
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neon-or-combine.ll
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neon-perm.ll
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neon-scalar-by-elem-fma.ll
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neon-scalar-copy.ll
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neon-shift-left-long.ll
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neon-truncStore-extLoad.ll
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nzcv-save.ll
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paired-load.ll
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PBQP.ll
[AArch64] Reenable the PBQP test now that the leak issue has been fixed.
2014-09-11 10:39:52 +00:00
pic-eh-stubs.ll
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postra-mi-sched.ll
[AArch64] Enable post-RA MI scheduler.
2014-09-12 17:40:39 +00:00
ragreedy-csr.ll
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rbit.ll
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regress-bitcast-formals.ll
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regress-f128csel-flags.ll
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regress-fp128-livein.ll
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regress-tail-livereg.ll
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regress-tblgen-chains.ll
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regress-w29-reserved-with-fp.ll
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remat.ll
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returnaddr.ll
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rm_redundant_cmp.ll
Optimize sext/zext insertion algorithm in back-end.
2014-09-19 05:30:35 +00:00
sdivpow2.ll
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setcc-takes-i32.ll
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sibling-call.ll
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sincos-expansion.ll
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sincospow-vector-expansion.ll
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stack_guard_remat.ll
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stack-guard-remat-bitcast.ll
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tail-call.ll
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tailcall-fastisel.ll
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tbz-tbnz.ll
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trunc-v1i64.ll
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tst-br.ll
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zero-reg.ll
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