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llvm-6502/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
David Majnemer c5edbea4e7 [InstCombine] (mul nsw 1, INT_MIN) != (shl nsw 1, 31) 
Multiplying INT_MIN by 1 doesn't trigger nsw.  However, shifting 1 into
the sign bit *does* trigger nsw.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235250 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-18 04:41:30 +00:00

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