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https://github.com/c64scene-ar/llvm-6502.git
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e68ea060c7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98224 91177308-0d34-0410-b5e6-96231b3b80d8
371 lines
12 KiB
C++
371 lines
12 KiB
C++
//===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs global common subexpression elimination on machine
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// instructions using a scoped hash table based value numbering scheme. It
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// must be run while the machine function is still in SSA form.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "machine-cse"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/ADT/ScopedHashTable.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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STATISTIC(NumCoalesces, "Number of copies coalesced");
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STATISTIC(NumCSEs, "Number of common subexpression eliminated");
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namespace {
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class MachineCSE : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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AliasAnalysis *AA;
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MachineDominatorTree *DT;
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MachineRegisterInfo *MRI;
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public:
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static char ID; // Pass identification
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MachineCSE() : MachineFunctionPass(&ID), CurrVN(0) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<AliasAnalysis>();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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private:
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unsigned CurrVN;
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ScopedHashTable<MachineInstr*, unsigned, MachineInstrExpressionTrait> VNT;
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SmallVector<MachineInstr*, 64> Exps;
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bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
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bool isPhysDefTriviallyDead(unsigned Reg,
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MachineBasicBlock::const_iterator I,
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MachineBasicBlock::const_iterator E);
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bool hasLivePhysRegDefUse(MachineInstr *MI, MachineBasicBlock *MBB);
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bool isCSECandidate(MachineInstr *MI);
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bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
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MachineInstr *CSMI, MachineInstr *MI);
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bool ProcessBlock(MachineDomTreeNode *Node);
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};
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} // end anonymous namespace
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char MachineCSE::ID = 0;
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static RegisterPass<MachineCSE>
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X("machine-cse", "Machine Common Subexpression Elimination");
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FunctionPass *llvm::createMachineCSEPass() { return new MachineCSE(); }
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bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
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MachineBasicBlock *MBB) {
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bool Changed = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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if (!MRI->hasOneUse(Reg))
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// Only coalesce single use copies. This ensure the copy will be
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// deleted.
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continue;
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MachineInstr *DefMI = MRI->getVRegDef(Reg);
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if (DefMI->getParent() != MBB)
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continue;
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (TII->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
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TargetRegisterInfo::isVirtualRegister(SrcReg) &&
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!SrcSubIdx && !DstSubIdx) {
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const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC);
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if (!NewRC)
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continue;
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DEBUG(dbgs() << "Coalescing: " << *DefMI);
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DEBUG(dbgs() << "*** to: " << *MI);
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MO.setReg(SrcReg);
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if (NewRC != SRC)
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MRI->setRegClass(SrcReg, NewRC);
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DefMI->eraseFromParent();
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++NumCoalesces;
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Changed = true;
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}
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}
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return Changed;
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}
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bool MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
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MachineBasicBlock::const_iterator I,
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MachineBasicBlock::const_iterator E) {
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unsigned LookAheadLeft = 5;
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while (LookAheadLeft--) {
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if (I == E)
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// Reached end of block, register is obviously dead.
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return true;
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if (I->isDebugValue()) {
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// These must not count against the limit.
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++LookAheadLeft;
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++I;
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continue;
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}
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bool SeenDef = false;
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = I->getOperand(i);
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if (!MO.isReg() || !MO.getReg())
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continue;
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if (!TRI->regsOverlap(MO.getReg(), Reg))
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continue;
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if (MO.isUse())
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return false;
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SeenDef = true;
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}
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if (SeenDef)
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// See a def of Reg (or an alias) before encountering any use, it's
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// trivially dead.
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return true;
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++I;
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}
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return false;
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}
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/// hasLivePhysRegDefUse - Return true if the specified instruction read / write
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/// physical registers (except for dead defs of physical registers).
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bool MachineCSE::hasLivePhysRegDefUse(MachineInstr *MI, MachineBasicBlock *MBB){
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unsigned PhysDef = 0;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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if (MO.isUse())
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// Can't touch anything to read a physical register.
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return true;
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if (MO.isDead())
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// If the def is dead, it's ok.
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continue;
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// Ok, this is a physical register def that's not marked "dead". That's
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// common since this pass is run before livevariables. We can scan
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// forward a few instructions and check if it is obviously dead.
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if (PhysDef)
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// Multiple physical register defs. These are rare, forget about it.
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return true;
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PhysDef = Reg;
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}
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}
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if (PhysDef) {
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MachineBasicBlock::iterator I = MI; I = llvm::next(I);
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if (!isPhysDefTriviallyDead(PhysDef, I, MBB->end()))
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return true;
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}
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return false;
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}
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static bool isCopy(const MachineInstr *MI, const TargetInstrInfo *TII) {
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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return TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) ||
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MI->isExtractSubreg() || MI->isInsertSubreg() || MI->isSubregToReg();
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}
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bool MachineCSE::isCSECandidate(MachineInstr *MI) {
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if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
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MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
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return false;
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// Ignore copies.
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if (isCopy(MI, TII))
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return false;
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// Ignore stuff that we obviously can't move.
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
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TID.hasUnmodeledSideEffects())
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return false;
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if (TID.mayLoad()) {
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// Okay, this instruction does a load. As a refinement, we allow the target
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// to decide whether the loaded value is actually a constant. If so, we can
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// actually use it as a load.
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if (!MI->isInvariantLoad(AA))
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// FIXME: we should be able to hoist loads with no other side effects if
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// there are no other instructions which can change memory in this loop.
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// This is a trivial form of alias analysis.
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return false;
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}
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return true;
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}
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/// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
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/// common expression that defines Reg.
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bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
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MachineInstr *CSMI, MachineInstr *MI) {
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// FIXME: Heuristics that works around the lack the live range splitting.
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// Heuristics #1: Don't cse "cheap" computating if the def is not local or in an
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// immediate predecessor. We don't want to increase register pressure and end up
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// causing other computation to be spilled.
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if (MI->getDesc().isAsCheapAsAMove()) {
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MachineBasicBlock *CSBB = CSMI->getParent();
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MachineBasicBlock *BB = MI->getParent();
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if (CSBB != BB &&
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find(CSBB->succ_begin(), CSBB->succ_end(), BB) == CSBB->succ_end())
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return false;
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}
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// Heuristics #2: If the expression doesn't not use a vr and the only use
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// of the redundant computation are copies, do not cse.
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bool HasVRegUse = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isUse() && MO.getReg() &&
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TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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HasVRegUse = true;
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break;
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}
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}
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if (!HasVRegUse) {
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bool HasNonCopyUse = false;
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for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
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E = MRI->use_nodbg_end(); I != E; ++I) {
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MachineInstr *Use = &*I;
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// Ignore copies.
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if (!isCopy(Use, TII)) {
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HasNonCopyUse = true;
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break;
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}
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}
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if (!HasNonCopyUse)
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return false;
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}
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// Heuristics #3: If the common subexpression is used by PHIs, do not reuse
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// it unless the defined value is already used in the BB of the new use.
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bool HasPHI = false;
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SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
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for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
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E = MRI->use_nodbg_end(); I != E; ++I) {
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MachineInstr *Use = &*I;
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HasPHI |= Use->isPHI();
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CSBBs.insert(Use->getParent());
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}
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if (!HasPHI)
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return true;
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return CSBBs.count(MI->getParent());
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}
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bool MachineCSE::ProcessBlock(MachineDomTreeNode *Node) {
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bool Changed = false;
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SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
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ScopedHashTableScope<MachineInstr*, unsigned,
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MachineInstrExpressionTrait> VNTS(VNT);
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MachineBasicBlock *MBB = Node->getBlock();
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
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MachineInstr *MI = &*I;
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++I;
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if (!isCSECandidate(MI))
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continue;
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bool FoundCSE = VNT.count(MI);
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if (!FoundCSE) {
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// Look for trivial copy coalescing opportunities.
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if (PerformTrivialCoalescing(MI, MBB))
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FoundCSE = VNT.count(MI);
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}
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// FIXME: commute commutable instructions?
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// If the instruction defines a physical register and the value *may* be
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// used, then it's not safe to replace it with a common subexpression.
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if (FoundCSE && hasLivePhysRegDefUse(MI, MBB))
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FoundCSE = false;
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if (!FoundCSE) {
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VNT.insert(MI, CurrVN++);
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Exps.push_back(MI);
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continue;
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}
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// Found a common subexpression, eliminate it.
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unsigned CSVN = VNT.lookup(MI);
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MachineInstr *CSMI = Exps[CSVN];
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DEBUG(dbgs() << "Examining: " << *MI);
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DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
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// Check if it's profitable to perform this CSE.
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bool DoCSE = true;
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unsigned NumDefs = MI->getDesc().getNumDefs();
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for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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unsigned OldReg = MO.getReg();
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unsigned NewReg = CSMI->getOperand(i).getReg();
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if (OldReg == NewReg)
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continue;
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assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
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TargetRegisterInfo::isVirtualRegister(NewReg) &&
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"Do not CSE physical register defs!");
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if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
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DoCSE = false;
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break;
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}
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CSEPairs.push_back(std::make_pair(OldReg, NewReg));
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--NumDefs;
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}
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// Actually perform the elimination.
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if (DoCSE) {
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for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i)
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MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
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MI->eraseFromParent();
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++NumCSEs;
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} else {
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DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
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VNT.insert(MI, CurrVN++);
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Exps.push_back(MI);
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}
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CSEPairs.clear();
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}
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// Recursively call ProcessBlock with childred.
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const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
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for (unsigned i = 0, e = Children.size(); i != e; ++i)
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Changed |= ProcessBlock(Children[i]);
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return Changed;
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}
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bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getTarget().getInstrInfo();
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TRI = MF.getTarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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AA = &getAnalysis<AliasAnalysis>();
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DT = &getAnalysis<MachineDominatorTree>();
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return ProcessBlock(DT->getRootNode());
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}
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