llvm-6502/test/MC/Disassembler/ARM64
2014-04-09 14:43:01 +00:00
..
advsimd.txt
arithmetic.txt [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 2014-04-09 14:42:11 +00:00
basic-a64-undefined.txt [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 2014-04-09 14:42:11 +00:00
bitfield.txt
branch.txt
canonical-form.txt [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 2014-04-09 14:43:01 +00:00
crc32.txt
crypto.txt
invalid-logical.txt
lit.local.cfg
logical.txt
memory.txt [ARM64] STRHro and STRBro were not being decoded at all. 2014-04-09 14:41:49 +00:00
scalar-fp.txt
system.txt [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS. 2014-04-09 14:42:42 +00:00