llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-09 13:33:17 +00:00

History

Marek Olsak a95296a86e R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI

This can happen when a REV instruction is commuted.

The trick is not to define the _vi versions of instructions, which has these
consequences:
- code generation will always fail if a pseudo cannot be lowered
  (very useful to catch bugs where an unsupported instruction somehow makes
   it to the printer)
- ability to query if a pseudo can be lowered, which is done in commuteOpcode
  to prevent REV from commuting to non-REV on VI

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227990 91177308-0d34-0410-b5e6-96231b3b80d8

2015-02-03 17:38:12 +00:00

Analysis

ValueTracking: Make isSafeToSpeculativelyExecute a little cleaner

2015-02-01 19:10:19 +00:00

AsmParser

IR: Split out DebugInfoMetadata.h, NFC

2015-02-02 18:53:21 +00:00

Bitcode

Propagate a better error message to the C api.

2015-02-03 01:53:03 +00:00

CodeGen

Only access TLOF via the TargetMachine, not TargetLowering.