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aab6231cd9
Otherwise the legalizer would just scalarize everything. Support for mulhi in the targets isn't that great yet so on most targets we get exactly the same scalarized output. Add a test for x86 vector udiv. I had to disable the mulhi nodes on ARM because there aren't any patterns for it. As far as I know ARM has instructions for getting the high part of a multiply so this should be fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207315 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
913 B
LLVM
46 lines
913 B
LLVM
; RUN: llc -march=x86-64 -mcpu=core2 < %s | FileCheck %s -check-prefix=SSE
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; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX
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define <4 x i32> @test1(<4 x i32> %a) {
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%div = udiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %div
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; SSE-LABEL: test1:
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; SSE: pmuludq
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; SSE: pshufd $57
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; SSE: pmuludq
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; SSE: shufps $-35
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; SSE: psubd
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; SSE: psrld $1
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; SSE: padd
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; SSE: psrld $2
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; AVX-LABEL: test1:
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; AVX: vpmuludq
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; AVX: vpshufd $57
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; AVX: vpmuludq
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; AVX: vshufps $-35
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; AVX: vpsubd
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; AVX: vpsrld $1
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; AVX: vpadd
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; AVX: vpsrld $2
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}
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define <8 x i32> @test2(<8 x i32> %a) {
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%div = udiv <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
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ret <8 x i32> %div
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; AVX-LABEL: test2:
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; AVX: vpermd
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; AVX: vpmuludq
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; AVX: vshufps $-35
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; AVX: vpmuludq
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; AVX: vshufps $-35
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; AVX: vpsubd
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; AVX: vpsrld $1
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; AVX: vpadd
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; AVX: vpsrld $2
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}
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; TODO: sdiv -> pmuldq
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