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documentation that this module needs to be made independent of the register file description of the current target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13125 91177308-0d34-0410-b5e6-96231b3b80d8
736 lines
27 KiB
C++
736 lines
27 KiB
C++
//===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Scheduling graph based on SSA graph plus extra dependence edges capturing
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// dependences due to machine resources (machine registers, CC registers, and
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// any others).
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//
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//===----------------------------------------------------------------------===//
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#include "SchedGraph.h"
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#include "llvm/Function.h"
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#include "llvm/iOther.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "../../Target/SparcV9/SparcV9RegInfo.h"
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#include "Support/STLExtras.h"
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namespace llvm {
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//*********************** Internal Data Structures *************************/
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// The following two types need to be classes, not typedefs, so we can use
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// opaque declarations in SchedGraph.h
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//
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struct RefVec: public std::vector<std::pair<SchedGraphNode*, int> > {
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typedef std::vector<std::pair<SchedGraphNode*,int> >::iterator iterator;
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typedef
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std::vector<std::pair<SchedGraphNode*,int> >::const_iterator const_iterator;
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};
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struct RegToRefVecMap: public hash_map<int, RefVec> {
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typedef hash_map<int, RefVec>:: iterator iterator;
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typedef hash_map<int, RefVec>::const_iterator const_iterator;
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};
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struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
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typedef hash_map<const Value*, RefVec>:: iterator iterator;
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typedef hash_map<const Value*, RefVec>::const_iterator const_iterator;
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};
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//
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// class SchedGraphNode
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//
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SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
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int indexInBB, const TargetMachine& Target)
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: SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) {
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if (mbb) {
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MachineBasicBlock::iterator I = MBB->begin();
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std::advance(I, indexInBB);
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MI = I;
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MachineOpCode mopCode = MI->getOpcode();
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latency = Target.getInstrInfo().hasResultInterlock(mopCode)
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? Target.getInstrInfo().minLatency(mopCode)
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: Target.getInstrInfo().maxLatency(mopCode);
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}
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}
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//
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// Method: SchedGraphNode Destructor
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//
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// Description:
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// Free memory allocated by the SchedGraphNode object.
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//
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// Notes:
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// Do not delete the edges here. The base class will take care of that.
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// Only handle subclass specific stuff here (where currently there is
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// none).
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//
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SchedGraphNode::~SchedGraphNode() {
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}
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//
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// class SchedGraph
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//
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SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
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: MBB(mbb) {
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buildGraph(target);
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}
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//
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// Method: SchedGraph Destructor
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//
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// Description:
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// This method deletes memory allocated by the SchedGraph object.
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//
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// Notes:
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// Do not delete the graphRoot or graphLeaf here. The base class handles
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// that bit of work.
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//
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SchedGraph::~SchedGraph() {
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for (const_iterator I = begin(); I != end(); ++I)
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delete I->second;
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}
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void SchedGraph::dump() const {
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std::cerr << " Sched Graph for Basic Block: "
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<< MBB.getBasicBlock()->getName()
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<< " (" << MBB.getBasicBlock() << ")"
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<< "\n\n Actual Root nodes: ";
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for (SchedGraphNodeCommon::const_iterator I = graphRoot->beginOutEdges(),
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E = graphRoot->endOutEdges();
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I != E; ++I) {
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std::cerr << (*I)->getSink ()->getNodeId ();
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if (I + 1 != E) { std::cerr << ", "; }
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}
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std::cerr << "\n Graph Nodes:\n";
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for (const_iterator I = begin(), E = end(); I != E; ++I)
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std::cerr << "\n" << *I->second;
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std::cerr << "\n";
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}
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void SchedGraph::addDummyEdges() {
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assert(graphRoot->getNumOutEdges() == 0);
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for (const_iterator I=begin(); I != end(); ++I) {
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SchedGraphNode* node = (*I).second;
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assert(node != graphRoot && node != graphLeaf);
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if (node->beginInEdges() == node->endInEdges())
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(void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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if (node->beginOutEdges() == node->endOutEdges())
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(void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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void SchedGraph::addCDEdges(const TerminatorInst* term,
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const TargetMachine& target) {
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const TargetInstrInfo& mii = target.getInstrInfo();
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MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
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// Find the first branch instr in the sequence of machine instrs for term
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//
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unsigned first = 0;
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while (! mii.isBranch(termMvec[first]->getOpcode()) &&
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! mii.isReturn(termMvec[first]->getOpcode()))
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++first;
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assert(first < termMvec.size() &&
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"No branch instructions for terminator? Ok, but weird!");
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if (first == termMvec.size())
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return;
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SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
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// Add CD edges from each instruction in the sequence to the
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// *last preceding* branch instr. in the sequence
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// Use a latency of 0 because we only need to prevent out-of-order issue.
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//
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for (unsigned i = termMvec.size(); i > first+1; --i) {
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SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
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assert(toNode && "No node for instr generated for branch/ret?");
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for (unsigned j = i-1; j != 0; --j)
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if (mii.isBranch(termMvec[j-1]->getOpcode()) ||
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mii.isReturn(termMvec[j-1]->getOpcode())) {
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SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
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assert(brNode && "No node for instr generated for branch/ret?");
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(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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break; // only one incoming edge is enough
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}
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}
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// Add CD edges from each instruction preceding the first branch
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// to the first branch. Use a latency of 0 as above.
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//
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for (unsigned i = first; i != 0; --i) {
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SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
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assert(fromNode && "No node for instr generated for branch?");
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(void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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// Now add CD edges to the first branch instruction in the sequence from
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// all preceding instructions in the basic block. Use 0 latency again.
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//
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
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if (&*I == termMvec[first]) // reached the first branch
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break;
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SchedGraphNode* fromNode = getGraphNodeForInstr(I);
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if (fromNode == NULL)
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continue; // dummy instruction, e.g., PHI
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(void) new SchedGraphEdge(fromNode, firstBrNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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// If we find any other machine instructions (other than due to
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// the terminator) that also have delay slots, add an outgoing edge
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// from the instruction to the instructions in the delay slots.
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//
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unsigned d = mii.getNumDelaySlots(I->getOpcode());
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MachineBasicBlock::iterator J = I; ++J;
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for (unsigned j=1; j <= d; j++, ++J) {
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SchedGraphNode* toNode = this->getGraphNodeForInstr(J);
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assert(toNode && "No node for machine instr in delay slot?");
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(void) new SchedGraphEdge(fromNode, toNode,
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SchedGraphEdge::CtrlDep,
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SchedGraphEdge::NonDataDep, 0);
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}
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}
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}
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static const int SG_LOAD_REF = 0;
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static const int SG_STORE_REF = 1;
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static const int SG_CALL_REF = 2;
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static const unsigned int SG_DepOrderArray[][3] = {
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{ SchedGraphEdge::NonDataDep,
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SchedGraphEdge::AntiDep,
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SchedGraphEdge::AntiDep },
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{ SchedGraphEdge::TrueDep,
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SchedGraphEdge::OutputDep,
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SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
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{ SchedGraphEdge::TrueDep,
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SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
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SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
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| SchedGraphEdge::OutputDep }
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};
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// Add a dependence edge between every pair of machine load/store/call
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// instructions, where at least one is a store or a call.
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// Use latency 1 just to ensure that memory operations are ordered;
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// latency does not otherwise matter (true dependences enforce that).
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//
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void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
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const TargetMachine& target) {
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const TargetInstrInfo& mii = target.getInstrInfo();
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// Instructions in memNodeVec are in execution order within the basic block,
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// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
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//
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for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) {
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MachineOpCode fromOpCode = memNodeVec[im]->getOpcode();
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int fromType = (mii.isCall(fromOpCode)? SG_CALL_REF
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: (mii.isLoad(fromOpCode)? SG_LOAD_REF
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: SG_STORE_REF));
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for (unsigned jm=im+1; jm < NM; jm++) {
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MachineOpCode toOpCode = memNodeVec[jm]->getOpcode();
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int toType = (mii.isCall(toOpCode)? SG_CALL_REF
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: (mii.isLoad(toOpCode)? SG_LOAD_REF
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: SG_STORE_REF));
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if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
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(void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
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SchedGraphEdge::MemoryDep,
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SG_DepOrderArray[fromType][toType], 1);
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}
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}
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}
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// Add edges from/to CC reg instrs to/from call instrs.
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// Essentially this prevents anything that sets or uses a CC reg from being
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// reordered w.r.t. a call.
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// Use a latency of 0 because we only need to prevent out-of-order issue,
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// like with control dependences.
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//
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void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
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const TargetMachine& target) {
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const TargetInstrInfo& mii = target.getInstrInfo();
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// Instructions in memNodeVec are in execution order within the basic block,
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// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
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//
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for (unsigned ic=0, NC=callDepNodeVec.size(); ic < NC; ic++)
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if (mii.isCall(callDepNodeVec[ic]->getOpcode())) {
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// Add SG_CALL_REF edges from all preds to this instruction.
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for (unsigned jc=0; jc < ic; jc++)
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(void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
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SchedGraphEdge::MachineRegister,
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MachineIntRegsRID, 0);
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// And do the same from this instruction to all successors.
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for (unsigned jc=ic+1; jc < NC; jc++)
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(void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc],
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SchedGraphEdge::MachineRegister,
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MachineIntRegsRID, 0);
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}
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#ifdef CALL_DEP_NODE_VEC_CANNOT_WORK
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// Find the call instruction nodes and put them in a vector.
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std::vector<SchedGraphNode*> callNodeVec;
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for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
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if (mii.isCall(memNodeVec[im]->getOpcode()))
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callNodeVec.push_back(memNodeVec[im]);
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// Now walk the entire basic block, looking for CC instructions *and*
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// call instructions, and keep track of the order of the instructions.
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// Use the call node vec to quickly find earlier and later call nodes
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// relative to the current CC instruction.
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//
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int lastCallNodeIdx = -1;
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for (unsigned i=0, N=bbMvec.size(); i < N; i++)
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if (mii.isCall(bbMvec[i]->getOpcode())) {
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++lastCallNodeIdx;
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for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
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if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
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break;
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assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
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}
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else if (mii.isCCInstr(bbMvec[i]->getOpcode())) {
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// Add incoming/outgoing edges from/to preceding/later calls
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SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
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int j=0;
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for ( ; j <= lastCallNodeIdx; j++)
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(void) new SchedGraphEdge(callNodeVec[j], ccNode,
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MachineCCRegsRID, 0);
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for ( ; j < (int) callNodeVec.size(); j++)
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(void) new SchedGraphEdge(ccNode, callNodeVec[j],
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MachineCCRegsRID, 0);
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}
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#endif
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}
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void SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
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const TargetMachine& target) {
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// This code assumes that two registers with different numbers are
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// not aliased!
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//
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for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
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I != regToRefVecMap.end(); ++I) {
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int regNum = (*I).first;
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RefVec& regRefVec = (*I).second;
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// regRefVec is ordered by control flow order in the basic block
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for (unsigned i=0; i < regRefVec.size(); ++i) {
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SchedGraphNode* node = regRefVec[i].first;
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unsigned int opNum = regRefVec[i].second;
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const MachineOperand& mop =
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node->getMachineInstr()->getExplOrImplOperand(opNum);
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bool isDef = mop.isDef() && !mop.isUse();
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bool isDefAndUse = mop.isDef() && mop.isUse();
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for (unsigned p=0; p < i; ++p) {
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SchedGraphNode* prevNode = regRefVec[p].first;
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if (prevNode != node) {
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unsigned int prevOpNum = regRefVec[p].second;
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const MachineOperand& prevMop =
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prevNode->getMachineInstr()->getExplOrImplOperand(prevOpNum);
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bool prevIsDef = prevMop.isDef() && !prevMop.isUse();
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bool prevIsDefAndUse = prevMop.isDef() && prevMop.isUse();
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if (isDef) {
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if (prevIsDef)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::OutputDep);
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if (!prevIsDef || prevIsDefAndUse)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::AntiDep);
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}
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if (prevIsDef)
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if (!isDef || isDefAndUse)
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new SchedGraphEdge(prevNode, node, regNum,
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SchedGraphEdge::TrueDep);
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}
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}
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}
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}
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}
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// Adds dependences to/from refNode from/to all other defs
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// in the basic block. refNode may be a use, a def, or both.
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// We do not consider other uses because we are not building use-use deps.
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//
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void SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
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const RefVec& defVec,
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const Value* defValue,
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bool refNodeIsDef,
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bool refNodeIsUse,
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const TargetMachine& target) {
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// Add true or output dep edges from all def nodes before refNode in BB.
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// Add anti or output dep edges to all def nodes after refNode.
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for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) {
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if ((*I).first == refNode)
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continue; // Dont add any self-loops
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if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
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// (*).first is before refNode
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if (refNodeIsDef && !refNodeIsUse)
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(void) new SchedGraphEdge((*I).first, refNode, defValue,
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SchedGraphEdge::OutputDep);
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if (refNodeIsUse)
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(void) new SchedGraphEdge((*I).first, refNode, defValue,
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SchedGraphEdge::TrueDep);
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} else {
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// (*).first is after refNode
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if (refNodeIsDef && !refNodeIsUse)
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(void) new SchedGraphEdge(refNode, (*I).first, defValue,
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SchedGraphEdge::OutputDep);
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if (refNodeIsUse)
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(void) new SchedGraphEdge(refNode, (*I).first, defValue,
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SchedGraphEdge::AntiDep);
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}
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}
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}
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void SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
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const ValueToDefVecMap& valueToDefVecMap,
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const TargetMachine& target) {
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SchedGraphNode* node = getGraphNodeForInstr(&MI);
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if (node == NULL)
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return;
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// Add edges for all operands of the machine instruction.
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//
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for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i) {
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switch (MI.getOperand(i).getType()) {
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case MachineOperand::MO_VirtualRegister:
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case MachineOperand::MO_CCRegister:
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if (const Value* srcI = MI.getOperand(i).getVRegValue()) {
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ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
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if (I != valueToDefVecMap.end())
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addEdgesForValue(node, I->second, srcI,
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MI.getOperand(i).isDef(), MI.getOperand(i).isUse(),
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target);
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}
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break;
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case MachineOperand::MO_MachineRegister:
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break;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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case MachineOperand::MO_PCRelativeDisp:
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case MachineOperand::MO_ConstantPoolIndex:
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break; // nothing to do for immediate fields
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default:
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assert(0 && "Unknown machine operand type in SchedGraph builder");
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break;
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}
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}
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// Add edges for values implicitly used by the machine instruction.
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// Examples include function arguments to a Call instructions or the return
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// value of a Ret instruction.
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//
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for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
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if (MI.getImplicitOp(i).isUse())
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if (const Value* srcI = MI.getImplicitRef(i)) {
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|
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
|
|
if (I != valueToDefVecMap.end())
|
|
addEdgesForValue(node, I->second, srcI,
|
|
MI.getImplicitOp(i).isDef(),
|
|
MI.getImplicitOp(i).isUse(), target);
|
|
}
|
|
}
|
|
|
|
|
|
void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
|
|
SchedGraphNode* node,
|
|
std::vector<SchedGraphNode*>& memNodeVec,
|
|
std::vector<SchedGraphNode*>& callDepNodeVec,
|
|
RegToRefVecMap& regToRefVecMap,
|
|
ValueToDefVecMap& valueToDefVecMap) {
|
|
const TargetInstrInfo& mii = target.getInstrInfo();
|
|
|
|
MachineOpCode opCode = node->getOpcode();
|
|
|
|
if (mii.isCall(opCode) || mii.isCCInstr(opCode))
|
|
callDepNodeVec.push_back(node);
|
|
|
|
if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
|
|
memNodeVec.push_back(node);
|
|
|
|
// Collect the register references and value defs. for explicit operands
|
|
//
|
|
const MachineInstr& MI = *node->getMachineInstr();
|
|
for (int i=0, numOps = (int) MI.getNumOperands(); i < numOps; i++) {
|
|
const MachineOperand& mop = MI.getOperand(i);
|
|
|
|
// if this references a register other than the hardwired
|
|
// "zero" register, record the reference.
|
|
if (mop.hasAllocatedReg()) {
|
|
unsigned regNum = mop.getReg();
|
|
|
|
// If this is not a dummy zero register, record the reference in order
|
|
if (regNum != target.getRegInfo().getZeroRegNum())
|
|
regToRefVecMap[mop.getReg()]
|
|
.push_back(std::make_pair(node, i));
|
|
|
|
// If this is a volatile register, add the instruction to callDepVec
|
|
// (only if the node is not already on the callDepVec!)
|
|
if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node)
|
|
{
|
|
unsigned rcid;
|
|
int regInClass = target.getRegInfo().getClassRegNum(regNum, rcid);
|
|
if (target.getRegInfo().getMachineRegClass(rcid)
|
|
->isRegVolatile(regInClass))
|
|
callDepNodeVec.push_back(node);
|
|
}
|
|
|
|
continue; // nothing more to do
|
|
}
|
|
|
|
// ignore all other non-def operands
|
|
if (!MI.getOperand(i).isDef())
|
|
continue;
|
|
|
|
// We must be defining a value.
|
|
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
|
|
mop.getType() == MachineOperand::MO_CCRegister)
|
|
&& "Do not expect any other kind of operand to be defined!");
|
|
assert(mop.getVRegValue() != NULL && "Null value being defined?");
|
|
|
|
valueToDefVecMap[mop.getVRegValue()].push_back(std::make_pair(node, i));
|
|
}
|
|
|
|
//
|
|
// Collect value defs. for implicit operands. They may have allocated
|
|
// physical registers also.
|
|
//
|
|
for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
|
|
const MachineOperand& mop = MI.getImplicitOp(i);
|
|
if (mop.hasAllocatedReg()) {
|
|
unsigned regNum = mop.getReg();
|
|
if (regNum != target.getRegInfo().getZeroRegNum())
|
|
regToRefVecMap[mop.getReg()]
|
|
.push_back(std::make_pair(node, i + MI.getNumOperands()));
|
|
continue; // nothing more to do
|
|
}
|
|
|
|
if (mop.isDef()) {
|
|
assert(MI.getImplicitRef(i) != NULL && "Null value being defined?");
|
|
valueToDefVecMap[MI.getImplicitRef(i)].push_back(
|
|
std::make_pair(node, -i));
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void SchedGraph::buildNodesForBB(const TargetMachine& target,
|
|
MachineBasicBlock& MBB,
|
|
std::vector<SchedGraphNode*>& memNodeVec,
|
|
std::vector<SchedGraphNode*>& callDepNodeVec,
|
|
RegToRefVecMap& regToRefVecMap,
|
|
ValueToDefVecMap& valueToDefVecMap) {
|
|
const TargetInstrInfo& mii = target.getInstrInfo();
|
|
|
|
// Build graph nodes for each VM instruction and gather def/use info.
|
|
// Do both those together in a single pass over all machine instructions.
|
|
unsigned i = 0;
|
|
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
|
|
++I, ++i)
|
|
if (!mii.isDummyPhiInstr(I->getOpcode())) {
|
|
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
|
|
noteGraphNodeForInstr(I, node);
|
|
|
|
// Remember all register references and value defs
|
|
findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
|
|
regToRefVecMap, valueToDefVecMap);
|
|
}
|
|
}
|
|
|
|
|
|
void SchedGraph::buildGraph(const TargetMachine& target) {
|
|
// Use this data structure to note all machine operands that compute
|
|
// ordinary LLVM values. These must be computed defs (i.e., instructions).
|
|
// Note that there may be multiple machine instructions that define
|
|
// each Value.
|
|
ValueToDefVecMap valueToDefVecMap;
|
|
|
|
// Use this data structure to note all memory instructions.
|
|
// We use this to add memory dependence edges without a second full walk.
|
|
std::vector<SchedGraphNode*> memNodeVec;
|
|
|
|
// Use this data structure to note all instructions that access physical
|
|
// registers that can be modified by a call (including call instructions)
|
|
std::vector<SchedGraphNode*> callDepNodeVec;
|
|
|
|
// Use this data structure to note any uses or definitions of
|
|
// machine registers so we can add edges for those later without
|
|
// extra passes over the nodes.
|
|
// The vector holds an ordered list of references to the machine reg,
|
|
// ordered according to control-flow order. This only works for a
|
|
// single basic block, hence the assertion. Each reference is identified
|
|
// by the pair: <node, operand-number>.
|
|
//
|
|
RegToRefVecMap regToRefVecMap;
|
|
|
|
// Make a dummy root node. We'll add edges to the real roots later.
|
|
graphRoot = new SchedGraphNode(0, NULL, -1, target);
|
|
graphLeaf = new SchedGraphNode(1, NULL, -1, target);
|
|
|
|
//----------------------------------------------------------------
|
|
// First add nodes for all the machine instructions in the basic block
|
|
// because this greatly simplifies identifying which edges to add.
|
|
// Do this one VM instruction at a time since the SchedGraphNode needs that.
|
|
// Also, remember the load/store instructions to add memory deps later.
|
|
//----------------------------------------------------------------
|
|
|
|
buildNodesForBB(target, MBB, memNodeVec, callDepNodeVec,
|
|
regToRefVecMap, valueToDefVecMap);
|
|
|
|
//----------------------------------------------------------------
|
|
// Now add edges for the following (all are incoming edges except (4)):
|
|
// (1) operands of the machine instruction, including hidden operands
|
|
// (2) machine register dependences
|
|
// (3) memory load/store dependences
|
|
// (3) other resource dependences for the machine instruction, if any
|
|
// (4) output dependences when multiple machine instructions define the
|
|
// same value; all must have been generated from a single VM instrn
|
|
// (5) control dependences to branch instructions generated for the
|
|
// terminator instruction of the BB. Because of delay slots and
|
|
// 2-way conditional branches, multiple CD edges are needed
|
|
// (see addCDEdges for details).
|
|
// Also, note any uses or defs of machine registers.
|
|
//
|
|
//----------------------------------------------------------------
|
|
|
|
// First, add edges to the terminator instruction of the basic block.
|
|
this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
|
|
|
|
// Then add memory dep edges: store->load, load->store, and store->store.
|
|
// Call instructions are treated as both load and store.
|
|
this->addMemEdges(memNodeVec, target);
|
|
|
|
// Then add edges between call instructions and CC set/use instructions
|
|
this->addCallDepEdges(callDepNodeVec, target);
|
|
|
|
// Then add incoming def-use (SSA) edges for each machine instruction.
|
|
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
|
|
addEdgesForInstruction(*I, valueToDefVecMap, target);
|
|
|
|
// Then add edges for dependences on machine registers
|
|
this->addMachineRegEdges(regToRefVecMap, target);
|
|
|
|
// Finally, add edges from the dummy root and to dummy leaf
|
|
this->addDummyEdges();
|
|
}
|
|
|
|
|
|
//
|
|
// class SchedGraphSet
|
|
//
|
|
SchedGraphSet::SchedGraphSet(const Function* _function,
|
|
const TargetMachine& target) :
|
|
function(_function) {
|
|
buildGraphsForMethod(function, target);
|
|
}
|
|
|
|
SchedGraphSet::~SchedGraphSet() {
|
|
// delete all the graphs
|
|
for(iterator I = begin(), E = end(); I != E; ++I)
|
|
delete *I; // destructor is a friend
|
|
}
|
|
|
|
|
|
void SchedGraphSet::dump() const {
|
|
std::cerr << "======== Sched graphs for function `" << function->getName()
|
|
<< "' ========\n\n";
|
|
|
|
for (const_iterator I=begin(); I != end(); ++I)
|
|
(*I)->dump();
|
|
|
|
std::cerr << "\n====== End graphs for function `" << function->getName()
|
|
<< "' ========\n\n";
|
|
}
|
|
|
|
|
|
void SchedGraphSet::buildGraphsForMethod(const Function *F,
|
|
const TargetMachine& target) {
|
|
MachineFunction &MF = MachineFunction::get(F);
|
|
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
|
|
addGraph(new SchedGraph(*I, target));
|
|
}
|
|
|
|
|
|
void SchedGraphEdge::print(std::ostream &os) const {
|
|
os << "edge [" << src->getNodeId() << "] -> ["
|
|
<< sink->getNodeId() << "] : ";
|
|
|
|
switch(depType) {
|
|
case SchedGraphEdge::CtrlDep:
|
|
os<< "Control Dep";
|
|
break;
|
|
case SchedGraphEdge::ValueDep:
|
|
os<< "Reg Value " << val;
|
|
break;
|
|
case SchedGraphEdge::MemoryDep:
|
|
os<< "Memory Dep";
|
|
break;
|
|
case SchedGraphEdge::MachineRegister:
|
|
os<< "Reg " << machineRegNum;
|
|
break;
|
|
case SchedGraphEdge::MachineResource:
|
|
os<<"Resource "<< resourceId;
|
|
break;
|
|
default:
|
|
assert(0);
|
|
break;
|
|
}
|
|
|
|
os << " : delay = " << minDelay << "\n";
|
|
}
|
|
|
|
void SchedGraphNode::print(std::ostream &os) const {
|
|
os << std::string(8, ' ')
|
|
<< "Node " << ID << " : "
|
|
<< "latency = " << latency << "\n" << std::string(12, ' ');
|
|
|
|
if (getMachineInstr() == NULL)
|
|
os << "(Dummy node)\n";
|
|
else {
|
|
os << *getMachineInstr() << "\n" << std::string(12, ' ');
|
|
os << inEdges.size() << " Incoming Edges:\n";
|
|
for (unsigned i=0, N = inEdges.size(); i < N; i++)
|
|
os << std::string(16, ' ') << *inEdges[i];
|
|
|
|
os << std::string(12, ' ') << outEdges.size()
|
|
<< " Outgoing Edges:\n";
|
|
for (unsigned i=0, N= outEdges.size(); i < N; i++)
|
|
os << std::string(16, ' ') << *outEdges[i];
|
|
}
|
|
}
|
|
|
|
} // End llvm namespace
|