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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113198 91177308-0d34-0410-b5e6-96231b3b80d8
1786 lines
62 KiB
C++
1786 lines
62 KiB
C++
//===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits a target specifier matcher for converting parsed
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// assembly operands in the MCInst structures.
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//
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// The input to the target specific matcher is a list of literal tokens and
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// operands. The target specific parser should generally eliminate any syntax
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// which is not relevant for matching; for example, comma tokens should have
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// already been consumed and eliminated by the parser. Most instructions will
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// end up with a single literal token (the instruction name) and some number of
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// operands.
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//
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// Some example inputs, for X86:
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// 'addl' (immediate ...) (register ...)
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// 'add' (immediate ...) (memory ...)
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// 'call' '*' %epc
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//
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// The assembly matcher is responsible for converting this input into a precise
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// machine instruction (i.e., an instruction with a well defined encoding). This
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// mapping has several properties which complicate matching:
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//
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// - It may be ambiguous; many architectures can legally encode particular
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// variants of an instruction in different ways (for example, using a smaller
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// encoding for small immediates). Such ambiguities should never be
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// arbitrarily resolved by the assembler, the assembler is always responsible
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// for choosing the "best" available instruction.
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//
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// - It may depend on the subtarget or the assembler context. Instructions
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// which are invalid for the current mode, but otherwise unambiguous (e.g.,
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// an SSE instruction in a file being assembled for i486) should be accepted
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// and rejected by the assembler front end. However, if the proper encoding
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// for an instruction is dependent on the assembler context then the matcher
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// is responsible for selecting the correct machine instruction for the
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// current mode.
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//
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// The core matching algorithm attempts to exploit the regularity in most
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// instruction sets to quickly determine the set of possibly matching
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// instructions, and the simplify the generated code. Additionally, this helps
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// to ensure that the ambiguities are intentionally resolved by the user.
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//
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// The matching is divided into two distinct phases:
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//
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// 1. Classification: Each operand is mapped to the unique set which (a)
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// contains it, and (b) is the largest such subset for which a single
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// instruction could match all members.
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//
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// For register classes, we can generate these subgroups automatically. For
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// arbitrary operands, we expect the user to define the classes and their
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// relations to one another (for example, 8-bit signed immediates as a
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// subset of 32-bit immediates).
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//
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// By partitioning the operands in this way, we guarantee that for any
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// tuple of classes, any single instruction must match either all or none
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// of the sets of operands which could classify to that tuple.
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//
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// In addition, the subset relation amongst classes induces a partial order
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// on such tuples, which we use to resolve ambiguities.
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//
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// FIXME: What do we do if a crazy case shows up where this is the wrong
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// resolution?
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//
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// 2. The input can now be treated as a tuple of classes (static tokens are
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// simple singleton sets). Each such tuple should generally map to a single
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// instruction (we currently ignore cases where this isn't true, whee!!!),
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// which we can emit a simple matcher for.
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//
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//===----------------------------------------------------------------------===//
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#include "AsmMatcherEmitter.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "StringMatcher.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include <list>
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#include <map>
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#include <set>
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using namespace llvm;
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static cl::opt<std::string>
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MatchPrefix("match-prefix", cl::init(""),
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cl::desc("Only match instructions with the given prefix"));
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/// FlattenVariants - Flatten an .td file assembly string by selecting the
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/// variant at index \arg N.
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static std::string FlattenVariants(const std::string &AsmString,
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unsigned N) {
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StringRef Cur = AsmString;
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std::string Res = "";
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for (;;) {
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// Find the start of the next variant string.
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size_t VariantsStart = 0;
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for (size_t e = Cur.size(); VariantsStart != e; ++VariantsStart)
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if (Cur[VariantsStart] == '{' &&
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(VariantsStart == 0 || (Cur[VariantsStart-1] != '$' &&
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Cur[VariantsStart-1] != '\\')))
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break;
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// Add the prefix to the result.
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Res += Cur.slice(0, VariantsStart);
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if (VariantsStart == Cur.size())
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break;
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++VariantsStart; // Skip the '{'.
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// Scan to the end of the variants string.
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size_t VariantsEnd = VariantsStart;
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unsigned NestedBraces = 1;
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for (size_t e = Cur.size(); VariantsEnd != e; ++VariantsEnd) {
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if (Cur[VariantsEnd] == '}' && Cur[VariantsEnd-1] != '\\') {
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if (--NestedBraces == 0)
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break;
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} else if (Cur[VariantsEnd] == '{')
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++NestedBraces;
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}
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// Select the Nth variant (or empty).
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StringRef Selection = Cur.slice(VariantsStart, VariantsEnd);
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for (unsigned i = 0; i != N; ++i)
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Selection = Selection.split('|').second;
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Res += Selection.split('|').first;
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assert(VariantsEnd != Cur.size() &&
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"Unterminated variants in assembly string!");
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Cur = Cur.substr(VariantsEnd + 1);
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}
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return Res;
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}
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/// TokenizeAsmString - Tokenize a simplified assembly string.
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static void TokenizeAsmString(StringRef AsmString,
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SmallVectorImpl<StringRef> &Tokens) {
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unsigned Prev = 0;
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bool InTok = true;
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for (unsigned i = 0, e = AsmString.size(); i != e; ++i) {
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switch (AsmString[i]) {
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case '[':
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case ']':
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case '*':
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case '!':
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case ' ':
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case '\t':
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case ',':
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if (InTok) {
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Tokens.push_back(AsmString.slice(Prev, i));
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InTok = false;
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}
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if (!isspace(AsmString[i]) && AsmString[i] != ',')
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Tokens.push_back(AsmString.substr(i, 1));
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Prev = i + 1;
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break;
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case '\\':
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if (InTok) {
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Tokens.push_back(AsmString.slice(Prev, i));
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InTok = false;
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}
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++i;
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assert(i != AsmString.size() && "Invalid quoted character");
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Tokens.push_back(AsmString.substr(i, 1));
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Prev = i + 1;
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break;
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case '$': {
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// If this isn't "${", treat like a normal token.
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if (i + 1 == AsmString.size() || AsmString[i + 1] != '{') {
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if (InTok) {
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Tokens.push_back(AsmString.slice(Prev, i));
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InTok = false;
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}
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Prev = i;
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break;
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}
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if (InTok) {
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Tokens.push_back(AsmString.slice(Prev, i));
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InTok = false;
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}
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StringRef::iterator End =
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std::find(AsmString.begin() + i, AsmString.end(), '}');
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assert(End != AsmString.end() && "Missing brace in operand reference!");
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size_t EndPos = End - AsmString.begin();
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Tokens.push_back(AsmString.slice(i, EndPos+1));
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Prev = EndPos + 1;
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i = EndPos;
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break;
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}
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case '.':
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if (InTok) {
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Tokens.push_back(AsmString.slice(Prev, i));
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}
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Prev = i;
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InTok = true;
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break;
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default:
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InTok = true;
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}
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}
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if (InTok && Prev != AsmString.size())
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Tokens.push_back(AsmString.substr(Prev));
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}
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static bool IsAssemblerInstruction(StringRef Name,
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const CodeGenInstruction &CGI,
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const SmallVectorImpl<StringRef> &Tokens) {
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// Ignore "codegen only" instructions.
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if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
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return false;
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// Ignore pseudo ops.
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//
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// FIXME: This is a hack; can we convert these instructions to set the
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// "codegen only" bit instead?
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if (const RecordVal *Form = CGI.TheDef->getValue("Form"))
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if (Form->getValue()->getAsString() == "Pseudo")
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return false;
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// Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
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//
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// FIXME: This is a total hack.
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if (StringRef(Name).startswith("Int_") || StringRef(Name).endswith("_Int"))
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return false;
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// Ignore instructions with no .s string.
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//
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// FIXME: What are these?
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if (CGI.AsmString.empty())
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return false;
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// FIXME: Hack; ignore any instructions with a newline in them.
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if (std::find(CGI.AsmString.begin(),
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CGI.AsmString.end(), '\n') != CGI.AsmString.end())
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return false;
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// Ignore instructions with attributes, these are always fake instructions for
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// simplifying codegen.
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//
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// FIXME: Is this true?
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//
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// Also, check for instructions which reference the operand multiple times;
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// this implies a constraint we would not honor.
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std::set<std::string> OperandNames;
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for (unsigned i = 1, e = Tokens.size(); i < e; ++i) {
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if (Tokens[i][0] == '$' &&
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std::find(Tokens[i].begin(),
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Tokens[i].end(), ':') != Tokens[i].end()) {
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DEBUG({
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errs() << "warning: '" << Name << "': "
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<< "ignoring instruction; operand with attribute '"
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<< Tokens[i] << "'\n";
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});
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return false;
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}
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if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) {
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DEBUG({
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errs() << "warning: '" << Name << "': "
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<< "ignoring instruction with tied operand '"
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<< Tokens[i].str() << "'\n";
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});
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return false;
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}
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}
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return true;
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}
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namespace {
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struct SubtargetFeatureInfo;
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/// ClassInfo - Helper class for storing the information about a particular
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/// class of operands which can be matched.
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struct ClassInfo {
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enum ClassInfoKind {
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/// Invalid kind, for use as a sentinel value.
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Invalid = 0,
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/// The class for a particular token.
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Token,
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/// The (first) register class, subsequent register classes are
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/// RegisterClass0+1, and so on.
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RegisterClass0,
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/// The (first) user defined class, subsequent user defined classes are
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/// UserClass0+1, and so on.
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UserClass0 = 1<<16
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};
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/// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
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/// N) for the Nth user defined class.
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unsigned Kind;
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/// SuperClasses - The super classes of this class. Note that for simplicities
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/// sake user operands only record their immediate super class, while register
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/// operands include all superclasses.
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std::vector<ClassInfo*> SuperClasses;
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/// Name - The full class name, suitable for use in an enum.
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std::string Name;
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/// ClassName - The unadorned generic name for this class (e.g., Token).
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std::string ClassName;
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/// ValueName - The name of the value this class represents; for a token this
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/// is the literal token string, for an operand it is the TableGen class (or
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/// empty if this is a derived class).
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std::string ValueName;
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/// PredicateMethod - The name of the operand method to test whether the
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/// operand matches this class; this is not valid for Token or register kinds.
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std::string PredicateMethod;
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/// RenderMethod - The name of the operand method to add this operand to an
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/// MCInst; this is not valid for Token or register kinds.
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std::string RenderMethod;
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/// For register classes, the records for all the registers in this class.
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std::set<Record*> Registers;
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public:
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/// isRegisterClass() - Check if this is a register class.
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bool isRegisterClass() const {
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return Kind >= RegisterClass0 && Kind < UserClass0;
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}
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/// isUserClass() - Check if this is a user defined class.
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bool isUserClass() const {
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return Kind >= UserClass0;
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}
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/// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
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/// are related if they are in the same class hierarchy.
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bool isRelatedTo(const ClassInfo &RHS) const {
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// Tokens are only related to tokens.
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if (Kind == Token || RHS.Kind == Token)
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return Kind == Token && RHS.Kind == Token;
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// Registers classes are only related to registers classes, and only if
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// their intersection is non-empty.
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if (isRegisterClass() || RHS.isRegisterClass()) {
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if (!isRegisterClass() || !RHS.isRegisterClass())
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return false;
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std::set<Record*> Tmp;
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std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
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std::set_intersection(Registers.begin(), Registers.end(),
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RHS.Registers.begin(), RHS.Registers.end(),
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II);
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return !Tmp.empty();
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}
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// Otherwise we have two users operands; they are related if they are in the
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// same class hierarchy.
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//
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// FIXME: This is an oversimplification, they should only be related if they
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// intersect, however we don't have that information.
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assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
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const ClassInfo *Root = this;
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while (!Root->SuperClasses.empty())
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Root = Root->SuperClasses.front();
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const ClassInfo *RHSRoot = &RHS;
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while (!RHSRoot->SuperClasses.empty())
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RHSRoot = RHSRoot->SuperClasses.front();
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return Root == RHSRoot;
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}
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/// isSubsetOf - Test whether this class is a subset of \arg RHS;
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bool isSubsetOf(const ClassInfo &RHS) const {
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// This is a subset of RHS if it is the same class...
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if (this == &RHS)
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return true;
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// ... or if any of its super classes are a subset of RHS.
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for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
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ie = SuperClasses.end(); it != ie; ++it)
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if ((*it)->isSubsetOf(RHS))
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return true;
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return false;
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}
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/// operator< - Compare two classes.
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bool operator<(const ClassInfo &RHS) const {
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if (this == &RHS)
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return false;
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// Unrelated classes can be ordered by kind.
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if (!isRelatedTo(RHS))
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return Kind < RHS.Kind;
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switch (Kind) {
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case Invalid:
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assert(0 && "Invalid kind!");
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case Token:
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// Tokens are comparable by value.
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//
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// FIXME: Compare by enum value.
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return ValueName < RHS.ValueName;
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default:
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// This class preceeds the RHS if it is a proper subset of the RHS.
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if (isSubsetOf(RHS))
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return true;
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if (RHS.isSubsetOf(*this))
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return false;
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// Otherwise, order by name to ensure we have a total ordering.
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return ValueName < RHS.ValueName;
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}
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}
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};
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/// InstructionInfo - Helper class for storing the necessary information for an
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/// instruction which is capable of being matched.
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struct InstructionInfo {
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struct Operand {
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/// The unique class instance this operand should match.
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ClassInfo *Class;
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/// The original operand this corresponds to, if any.
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const CodeGenInstruction::OperandInfo *OperandInfo;
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};
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/// InstrName - The target name for this instruction.
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std::string InstrName;
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/// Instr - The instruction this matches.
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const CodeGenInstruction *Instr;
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/// AsmString - The assembly string for this instruction (with variants
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/// removed).
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std::string AsmString;
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/// Tokens - The tokenized assembly pattern that this instruction matches.
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SmallVector<StringRef, 4> Tokens;
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/// Operands - The operands that this instruction matches.
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SmallVector<Operand, 4> Operands;
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/// Predicates - The required subtarget features to match this instruction.
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SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
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/// ConversionFnKind - The enum value which is passed to the generated
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/// ConvertToMCInst to convert parsed operands into an MCInst for this
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/// function.
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std::string ConversionFnKind;
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/// operator< - Compare two instructions.
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bool operator<(const InstructionInfo &RHS) const {
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// The primary comparator is the instruction mnemonic.
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if (Tokens[0] != RHS.Tokens[0])
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return Tokens[0] < RHS.Tokens[0];
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if (Operands.size() != RHS.Operands.size())
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return Operands.size() < RHS.Operands.size();
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// Compare lexicographically by operand. The matcher validates that other
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// orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith().
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (*Operands[i].Class < *RHS.Operands[i].Class)
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return true;
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if (*RHS.Operands[i].Class < *Operands[i].Class)
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return false;
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}
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return false;
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}
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/// CouldMatchAmiguouslyWith - Check whether this instruction could
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/// ambiguously match the same set of operands as \arg RHS (without being a
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/// strictly superior match).
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bool CouldMatchAmiguouslyWith(const InstructionInfo &RHS) {
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// The number of operands is unambiguous.
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if (Operands.size() != RHS.Operands.size())
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return false;
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// Otherwise, make sure the ordering of the two instructions is unambiguous
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// by checking that either (a) a token or operand kind discriminates them,
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// or (b) the ordering among equivalent kinds is consistent.
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// Tokens and operand kinds are unambiguous (assuming a correct target
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// specific parser).
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for (unsigned i = 0, e = Operands.size(); i != e; ++i)
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if (Operands[i].Class->Kind != RHS.Operands[i].Class->Kind ||
|
|
Operands[i].Class->Kind == ClassInfo::Token)
|
|
if (*Operands[i].Class < *RHS.Operands[i].Class ||
|
|
*RHS.Operands[i].Class < *Operands[i].Class)
|
|
return false;
|
|
|
|
// Otherwise, this operand could commute if all operands are equivalent, or
|
|
// there is a pair of operands that compare less than and a pair that
|
|
// compare greater than.
|
|
bool HasLT = false, HasGT = false;
|
|
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
|
|
if (*Operands[i].Class < *RHS.Operands[i].Class)
|
|
HasLT = true;
|
|
if (*RHS.Operands[i].Class < *Operands[i].Class)
|
|
HasGT = true;
|
|
}
|
|
|
|
return !(HasLT ^ HasGT);
|
|
}
|
|
|
|
public:
|
|
void dump();
|
|
};
|
|
|
|
/// SubtargetFeatureInfo - Helper class for storing information on a subtarget
|
|
/// feature which participates in instruction matching.
|
|
struct SubtargetFeatureInfo {
|
|
/// \brief The predicate record for this feature.
|
|
Record *TheDef;
|
|
|
|
/// \brief An unique index assigned to represent this feature.
|
|
unsigned Index;
|
|
|
|
/// \brief The name of the enumerated constant identifying this feature.
|
|
std::string EnumName;
|
|
};
|
|
|
|
class AsmMatcherInfo {
|
|
public:
|
|
/// The tablegen AsmParser record.
|
|
Record *AsmParser;
|
|
|
|
/// The AsmParser "CommentDelimiter" value.
|
|
std::string CommentDelimiter;
|
|
|
|
/// The AsmParser "RegisterPrefix" value.
|
|
std::string RegisterPrefix;
|
|
|
|
/// The classes which are needed for matching.
|
|
std::vector<ClassInfo*> Classes;
|
|
|
|
/// The information on the instruction to match.
|
|
std::vector<InstructionInfo*> Instructions;
|
|
|
|
/// Map of Register records to their class information.
|
|
std::map<Record*, ClassInfo*> RegisterClasses;
|
|
|
|
/// Map of Predicate records to their subtarget information.
|
|
std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
|
|
|
|
private:
|
|
/// Map of token to class information which has already been constructed.
|
|
std::map<std::string, ClassInfo*> TokenClasses;
|
|
|
|
/// Map of RegisterClass records to their class information.
|
|
std::map<Record*, ClassInfo*> RegisterClassClasses;
|
|
|
|
/// Map of AsmOperandClass records to their class information.
|
|
std::map<Record*, ClassInfo*> AsmOperandClasses;
|
|
|
|
private:
|
|
/// getTokenClass - Lookup or create the class for the given token.
|
|
ClassInfo *getTokenClass(StringRef Token);
|
|
|
|
/// getOperandClass - Lookup or create the class for the given operand.
|
|
ClassInfo *getOperandClass(StringRef Token,
|
|
const CodeGenInstruction::OperandInfo &OI);
|
|
|
|
/// getSubtargetFeature - Lookup or create the subtarget feature info for the
|
|
/// given operand.
|
|
SubtargetFeatureInfo *getSubtargetFeature(Record *Def) {
|
|
assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
|
|
|
|
SubtargetFeatureInfo *&Entry = SubtargetFeatures[Def];
|
|
if (!Entry) {
|
|
Entry = new SubtargetFeatureInfo;
|
|
Entry->TheDef = Def;
|
|
Entry->Index = SubtargetFeatures.size() - 1;
|
|
Entry->EnumName = "Feature_" + Def->getName();
|
|
assert(Entry->Index < 32 && "Too many subtarget features!");
|
|
}
|
|
|
|
return Entry;
|
|
}
|
|
|
|
/// BuildRegisterClasses - Build the ClassInfo* instances for register
|
|
/// classes.
|
|
void BuildRegisterClasses(CodeGenTarget &Target,
|
|
std::set<std::string> &SingletonRegisterNames);
|
|
|
|
/// BuildOperandClasses - Build the ClassInfo* instances for user defined
|
|
/// operand classes.
|
|
void BuildOperandClasses(CodeGenTarget &Target);
|
|
|
|
public:
|
|
AsmMatcherInfo(Record *_AsmParser);
|
|
|
|
/// BuildInfo - Construct the various tables used during matching.
|
|
void BuildInfo(CodeGenTarget &Target);
|
|
};
|
|
|
|
}
|
|
|
|
void InstructionInfo::dump() {
|
|
errs() << InstrName << " -- " << "flattened:\"" << AsmString << '\"'
|
|
<< ", tokens:[";
|
|
for (unsigned i = 0, e = Tokens.size(); i != e; ++i) {
|
|
errs() << Tokens[i];
|
|
if (i + 1 != e)
|
|
errs() << ", ";
|
|
}
|
|
errs() << "]\n";
|
|
|
|
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
|
|
Operand &Op = Operands[i];
|
|
errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
|
|
if (Op.Class->Kind == ClassInfo::Token) {
|
|
errs() << '\"' << Tokens[i] << "\"\n";
|
|
continue;
|
|
}
|
|
|
|
if (!Op.OperandInfo) {
|
|
errs() << "(singleton register)\n";
|
|
continue;
|
|
}
|
|
|
|
const CodeGenInstruction::OperandInfo &OI = *Op.OperandInfo;
|
|
errs() << OI.Name << " " << OI.Rec->getName()
|
|
<< " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n";
|
|
}
|
|
}
|
|
|
|
static std::string getEnumNameForToken(StringRef Str) {
|
|
std::string Res;
|
|
|
|
for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
|
|
switch (*it) {
|
|
case '*': Res += "_STAR_"; break;
|
|
case '%': Res += "_PCT_"; break;
|
|
case ':': Res += "_COLON_"; break;
|
|
|
|
default:
|
|
if (isalnum(*it)) {
|
|
Res += *it;
|
|
} else {
|
|
Res += "_" + utostr((unsigned) *it) + "_";
|
|
}
|
|
}
|
|
}
|
|
|
|
return Res;
|
|
}
|
|
|
|
/// getRegisterRecord - Get the register record for \arg name, or 0.
|
|
static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) {
|
|
for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
|
|
const CodeGenRegister &Reg = Target.getRegisters()[i];
|
|
if (Name == Reg.TheDef->getValueAsString("AsmName"))
|
|
return Reg.TheDef;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
|
|
ClassInfo *&Entry = TokenClasses[Token];
|
|
|
|
if (!Entry) {
|
|
Entry = new ClassInfo();
|
|
Entry->Kind = ClassInfo::Token;
|
|
Entry->ClassName = "Token";
|
|
Entry->Name = "MCK_" + getEnumNameForToken(Token);
|
|
Entry->ValueName = Token;
|
|
Entry->PredicateMethod = "<invalid>";
|
|
Entry->RenderMethod = "<invalid>";
|
|
Classes.push_back(Entry);
|
|
}
|
|
|
|
return Entry;
|
|
}
|
|
|
|
ClassInfo *
|
|
AsmMatcherInfo::getOperandClass(StringRef Token,
|
|
const CodeGenInstruction::OperandInfo &OI) {
|
|
if (OI.Rec->isSubClassOf("RegisterClass")) {
|
|
ClassInfo *CI = RegisterClassClasses[OI.Rec];
|
|
|
|
if (!CI) {
|
|
PrintError(OI.Rec->getLoc(), "register class has no class info!");
|
|
throw std::string("ERROR: Missing register class!");
|
|
}
|
|
|
|
return CI;
|
|
}
|
|
|
|
assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
|
|
Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
|
|
ClassInfo *CI = AsmOperandClasses[MatchClass];
|
|
|
|
if (!CI) {
|
|
PrintError(OI.Rec->getLoc(), "operand has no match class!");
|
|
throw std::string("ERROR: Missing match class!");
|
|
}
|
|
|
|
return CI;
|
|
}
|
|
|
|
void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target,
|
|
std::set<std::string>
|
|
&SingletonRegisterNames) {
|
|
std::vector<CodeGenRegisterClass> RegisterClasses;
|
|
std::vector<CodeGenRegister> Registers;
|
|
|
|
RegisterClasses = Target.getRegisterClasses();
|
|
Registers = Target.getRegisters();
|
|
|
|
// The register sets used for matching.
|
|
std::set< std::set<Record*> > RegisterSets;
|
|
|
|
// Gather the defined sets.
|
|
for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
|
|
ie = RegisterClasses.end(); it != ie; ++it)
|
|
RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
|
|
it->Elements.end()));
|
|
|
|
// Add any required singleton sets.
|
|
for (std::set<std::string>::iterator it = SingletonRegisterNames.begin(),
|
|
ie = SingletonRegisterNames.end(); it != ie; ++it)
|
|
if (Record *Rec = getRegisterRecord(Target, *it))
|
|
RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
|
|
|
|
// Introduce derived sets where necessary (when a register does not determine
|
|
// a unique register set class), and build the mapping of registers to the set
|
|
// they should classify to.
|
|
std::map<Record*, std::set<Record*> > RegisterMap;
|
|
for (std::vector<CodeGenRegister>::iterator it = Registers.begin(),
|
|
ie = Registers.end(); it != ie; ++it) {
|
|
CodeGenRegister &CGR = *it;
|
|
// Compute the intersection of all sets containing this register.
|
|
std::set<Record*> ContainingSet;
|
|
|
|
for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
|
|
ie = RegisterSets.end(); it != ie; ++it) {
|
|
if (!it->count(CGR.TheDef))
|
|
continue;
|
|
|
|
if (ContainingSet.empty()) {
|
|
ContainingSet = *it;
|
|
} else {
|
|
std::set<Record*> Tmp;
|
|
std::swap(Tmp, ContainingSet);
|
|
std::insert_iterator< std::set<Record*> > II(ContainingSet,
|
|
ContainingSet.begin());
|
|
std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(),
|
|
II);
|
|
}
|
|
}
|
|
|
|
if (!ContainingSet.empty()) {
|
|
RegisterSets.insert(ContainingSet);
|
|
RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
|
|
}
|
|
}
|
|
|
|
// Construct the register classes.
|
|
std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
|
|
unsigned Index = 0;
|
|
for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
|
|
ie = RegisterSets.end(); it != ie; ++it, ++Index) {
|
|
ClassInfo *CI = new ClassInfo();
|
|
CI->Kind = ClassInfo::RegisterClass0 + Index;
|
|
CI->ClassName = "Reg" + utostr(Index);
|
|
CI->Name = "MCK_Reg" + utostr(Index);
|
|
CI->ValueName = "";
|
|
CI->PredicateMethod = ""; // unused
|
|
CI->RenderMethod = "addRegOperands";
|
|
CI->Registers = *it;
|
|
Classes.push_back(CI);
|
|
RegisterSetClasses.insert(std::make_pair(*it, CI));
|
|
}
|
|
|
|
// Find the superclasses; we could compute only the subgroup lattice edges,
|
|
// but there isn't really a point.
|
|
for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
|
|
ie = RegisterSets.end(); it != ie; ++it) {
|
|
ClassInfo *CI = RegisterSetClasses[*it];
|
|
for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
|
|
ie2 = RegisterSets.end(); it2 != ie2; ++it2)
|
|
if (*it != *it2 &&
|
|
std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
|
|
CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
|
|
}
|
|
|
|
// Name the register classes which correspond to a user defined RegisterClass.
|
|
for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
|
|
ie = RegisterClasses.end(); it != ie; ++it) {
|
|
ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
|
|
it->Elements.end())];
|
|
if (CI->ValueName.empty()) {
|
|
CI->ClassName = it->getName();
|
|
CI->Name = "MCK_" + it->getName();
|
|
CI->ValueName = it->getName();
|
|
} else
|
|
CI->ValueName = CI->ValueName + "," + it->getName();
|
|
|
|
RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
|
|
}
|
|
|
|
// Populate the map for individual registers.
|
|
for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
|
|
ie = RegisterMap.end(); it != ie; ++it)
|
|
this->RegisterClasses[it->first] = RegisterSetClasses[it->second];
|
|
|
|
// Name the register classes which correspond to singleton registers.
|
|
for (std::set<std::string>::iterator it = SingletonRegisterNames.begin(),
|
|
ie = SingletonRegisterNames.end(); it != ie; ++it) {
|
|
if (Record *Rec = getRegisterRecord(Target, *it)) {
|
|
ClassInfo *CI = this->RegisterClasses[Rec];
|
|
assert(CI && "Missing singleton register class info!");
|
|
|
|
if (CI->ValueName.empty()) {
|
|
CI->ClassName = Rec->getName();
|
|
CI->Name = "MCK_" + Rec->getName();
|
|
CI->ValueName = Rec->getName();
|
|
} else
|
|
CI->ValueName = CI->ValueName + "," + Rec->getName();
|
|
}
|
|
}
|
|
}
|
|
|
|
void AsmMatcherInfo::BuildOperandClasses(CodeGenTarget &Target) {
|
|
std::vector<Record*> AsmOperands;
|
|
AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass");
|
|
|
|
// Pre-populate AsmOperandClasses map.
|
|
for (std::vector<Record*>::iterator it = AsmOperands.begin(),
|
|
ie = AsmOperands.end(); it != ie; ++it)
|
|
AsmOperandClasses[*it] = new ClassInfo();
|
|
|
|
unsigned Index = 0;
|
|
for (std::vector<Record*>::iterator it = AsmOperands.begin(),
|
|
ie = AsmOperands.end(); it != ie; ++it, ++Index) {
|
|
ClassInfo *CI = AsmOperandClasses[*it];
|
|
CI->Kind = ClassInfo::UserClass0 + Index;
|
|
|
|
ListInit *Supers = (*it)->getValueAsListInit("SuperClasses");
|
|
for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
|
|
DefInit *DI = dynamic_cast<DefInit*>(Supers->getElement(i));
|
|
if (!DI) {
|
|
PrintError((*it)->getLoc(), "Invalid super class reference!");
|
|
continue;
|
|
}
|
|
|
|
ClassInfo *SC = AsmOperandClasses[DI->getDef()];
|
|
if (!SC)
|
|
PrintError((*it)->getLoc(), "Invalid super class reference!");
|
|
else
|
|
CI->SuperClasses.push_back(SC);
|
|
}
|
|
CI->ClassName = (*it)->getValueAsString("Name");
|
|
CI->Name = "MCK_" + CI->ClassName;
|
|
CI->ValueName = (*it)->getName();
|
|
|
|
// Get or construct the predicate method name.
|
|
Init *PMName = (*it)->getValueInit("PredicateMethod");
|
|
if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
|
|
CI->PredicateMethod = SI->getValue();
|
|
} else {
|
|
assert(dynamic_cast<UnsetInit*>(PMName) &&
|
|
"Unexpected PredicateMethod field!");
|
|
CI->PredicateMethod = "is" + CI->ClassName;
|
|
}
|
|
|
|
// Get or construct the render method name.
|
|
Init *RMName = (*it)->getValueInit("RenderMethod");
|
|
if (StringInit *SI = dynamic_cast<StringInit*>(RMName)) {
|
|
CI->RenderMethod = SI->getValue();
|
|
} else {
|
|
assert(dynamic_cast<UnsetInit*>(RMName) &&
|
|
"Unexpected RenderMethod field!");
|
|
CI->RenderMethod = "add" + CI->ClassName + "Operands";
|
|
}
|
|
|
|
AsmOperandClasses[*it] = CI;
|
|
Classes.push_back(CI);
|
|
}
|
|
}
|
|
|
|
AsmMatcherInfo::AsmMatcherInfo(Record *_AsmParser)
|
|
: AsmParser(_AsmParser),
|
|
CommentDelimiter(AsmParser->getValueAsString("CommentDelimiter")),
|
|
RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix"))
|
|
{
|
|
}
|
|
|
|
void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
|
|
// Parse the instructions; we need to do this first so that we can gather the
|
|
// singleton register classes.
|
|
std::set<std::string> SingletonRegisterNames;
|
|
|
|
const std::vector<const CodeGenInstruction*> &InstrList =
|
|
Target.getInstructionsByEnumValue();
|
|
|
|
for (unsigned i = 0, e = InstrList.size(); i != e; ++i) {
|
|
const CodeGenInstruction &CGI = *InstrList[i];
|
|
|
|
if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
|
|
continue;
|
|
|
|
OwningPtr<InstructionInfo> II(new InstructionInfo());
|
|
|
|
II->InstrName = CGI.TheDef->getName();
|
|
II->Instr = &CGI;
|
|
II->AsmString = FlattenVariants(CGI.AsmString, 0);
|
|
|
|
// Remove comments from the asm string.
|
|
if (!CommentDelimiter.empty()) {
|
|
size_t Idx = StringRef(II->AsmString).find(CommentDelimiter);
|
|
if (Idx != StringRef::npos)
|
|
II->AsmString = II->AsmString.substr(0, Idx);
|
|
}
|
|
|
|
TokenizeAsmString(II->AsmString, II->Tokens);
|
|
|
|
// Ignore instructions which shouldn't be matched.
|
|
if (!IsAssemblerInstruction(CGI.TheDef->getName(), CGI, II->Tokens))
|
|
continue;
|
|
|
|
// Collect singleton registers, if used.
|
|
if (!RegisterPrefix.empty()) {
|
|
for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) {
|
|
if (II->Tokens[i].startswith(RegisterPrefix)) {
|
|
StringRef RegName = II->Tokens[i].substr(RegisterPrefix.size());
|
|
Record *Rec = getRegisterRecord(Target, RegName);
|
|
|
|
if (!Rec) {
|
|
std::string Err = "unable to find register for '" + RegName.str() +
|
|
"' (which matches register prefix)";
|
|
throw TGError(CGI.TheDef->getLoc(), Err);
|
|
}
|
|
|
|
SingletonRegisterNames.insert(RegName);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Compute the require features.
|
|
ListInit *Predicates = CGI.TheDef->getValueAsListInit("Predicates");
|
|
for (unsigned i = 0, e = Predicates->getSize(); i != e; ++i) {
|
|
if (DefInit *Pred = dynamic_cast<DefInit*>(Predicates->getElement(i))) {
|
|
// Ignore OptForSize and OptForSpeed, they aren't really requirements,
|
|
// rather they are hints to isel.
|
|
//
|
|
// FIXME: Find better way to model this.
|
|
if (Pred->getDef()->getName() == "OptForSize" ||
|
|
Pred->getDef()->getName() == "OptForSpeed")
|
|
continue;
|
|
|
|
// FIXME: Total hack; for now, we just limit ourselves to In32BitMode
|
|
// and In64BitMode, because we aren't going to have the right feature
|
|
// masks for SSE and friends. We need to decide what we are going to do
|
|
// about CPU subtypes to implement this the right way.
|
|
if (Pred->getDef()->getName() != "In32BitMode" &&
|
|
Pred->getDef()->getName() != "In64BitMode")
|
|
continue;
|
|
|
|
II->RequiredFeatures.push_back(getSubtargetFeature(Pred->getDef()));
|
|
}
|
|
}
|
|
|
|
Instructions.push_back(II.take());
|
|
}
|
|
|
|
// Build info for the register classes.
|
|
BuildRegisterClasses(Target, SingletonRegisterNames);
|
|
|
|
// Build info for the user defined assembly operand classes.
|
|
BuildOperandClasses(Target);
|
|
|
|
// Build the instruction information.
|
|
for (std::vector<InstructionInfo*>::iterator it = Instructions.begin(),
|
|
ie = Instructions.end(); it != ie; ++it) {
|
|
InstructionInfo *II = *it;
|
|
|
|
// The first token of the instruction is the mnemonic, which must be a
|
|
// simple string.
|
|
assert(!II->Tokens.empty() && "Instruction has no tokens?");
|
|
StringRef Mnemonic = II->Tokens[0];
|
|
assert(Mnemonic[0] != '$' &&
|
|
(RegisterPrefix.empty() || !Mnemonic.startswith(RegisterPrefix)));
|
|
|
|
// Parse the tokens after the mnemonic.
|
|
for (unsigned i = 1, e = II->Tokens.size(); i != e; ++i) {
|
|
StringRef Token = II->Tokens[i];
|
|
|
|
// Check for singleton registers.
|
|
if (!RegisterPrefix.empty() && Token.startswith(RegisterPrefix)) {
|
|
StringRef RegName = II->Tokens[i].substr(RegisterPrefix.size());
|
|
InstructionInfo::Operand Op;
|
|
Op.Class = RegisterClasses[getRegisterRecord(Target, RegName)];
|
|
Op.OperandInfo = 0;
|
|
assert(Op.Class && Op.Class->Registers.size() == 1 &&
|
|
"Unexpected class for singleton register");
|
|
II->Operands.push_back(Op);
|
|
continue;
|
|
}
|
|
|
|
// Check for simple tokens.
|
|
if (Token[0] != '$') {
|
|
InstructionInfo::Operand Op;
|
|
Op.Class = getTokenClass(Token);
|
|
Op.OperandInfo = 0;
|
|
II->Operands.push_back(Op);
|
|
continue;
|
|
}
|
|
|
|
// Otherwise this is an operand reference.
|
|
StringRef OperandName;
|
|
if (Token[1] == '{')
|
|
OperandName = Token.substr(2, Token.size() - 3);
|
|
else
|
|
OperandName = Token.substr(1);
|
|
|
|
// Map this token to an operand. FIXME: Move elsewhere.
|
|
unsigned Idx;
|
|
try {
|
|
Idx = II->Instr->getOperandNamed(OperandName);
|
|
} catch(...) {
|
|
throw std::string("error: unable to find operand: '" +
|
|
OperandName.str() + "'");
|
|
}
|
|
|
|
// FIXME: This is annoying, the named operand may be tied (e.g.,
|
|
// XCHG8rm). What we want is the untied operand, which we now have to
|
|
// grovel for. Only worry about this for single entry operands, we have to
|
|
// clean this up anyway.
|
|
const CodeGenInstruction::OperandInfo *OI = &II->Instr->OperandList[Idx];
|
|
if (OI->Constraints[0].isTied()) {
|
|
unsigned TiedOp = OI->Constraints[0].getTiedOperand();
|
|
|
|
// The tied operand index is an MIOperand index, find the operand that
|
|
// contains it.
|
|
for (unsigned i = 0, e = II->Instr->OperandList.size(); i != e; ++i) {
|
|
if (II->Instr->OperandList[i].MIOperandNo == TiedOp) {
|
|
OI = &II->Instr->OperandList[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
assert(OI && "Unable to find tied operand target!");
|
|
}
|
|
|
|
InstructionInfo::Operand Op;
|
|
Op.Class = getOperandClass(Token, *OI);
|
|
Op.OperandInfo = OI;
|
|
II->Operands.push_back(Op);
|
|
}
|
|
}
|
|
|
|
// Reorder classes so that classes preceed super classes.
|
|
std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
|
|
}
|
|
|
|
static std::pair<unsigned, unsigned> *
|
|
GetTiedOperandAtIndex(SmallVectorImpl<std::pair<unsigned, unsigned> > &List,
|
|
unsigned Index) {
|
|
for (unsigned i = 0, e = List.size(); i != e; ++i)
|
|
if (Index == List[i].first)
|
|
return &List[i];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void EmitConvertToMCInst(CodeGenTarget &Target,
|
|
std::vector<InstructionInfo*> &Infos,
|
|
raw_ostream &OS) {
|
|
// Write the convert function to a separate stream, so we can drop it after
|
|
// the enum.
|
|
std::string ConvertFnBody;
|
|
raw_string_ostream CvtOS(ConvertFnBody);
|
|
|
|
// Function we have already generated.
|
|
std::set<std::string> GeneratedFns;
|
|
|
|
// Start the unified conversion function.
|
|
|
|
CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, "
|
|
<< "unsigned Opcode,\n"
|
|
<< " const SmallVectorImpl<MCParsedAsmOperand*"
|
|
<< "> &Operands) {\n";
|
|
CvtOS << " Inst.setOpcode(Opcode);\n";
|
|
CvtOS << " switch (Kind) {\n";
|
|
CvtOS << " default:\n";
|
|
|
|
// Start the enum, which we will generate inline.
|
|
|
|
OS << "// Unified function for converting operants to MCInst instances.\n\n";
|
|
OS << "enum ConversionKind {\n";
|
|
|
|
// TargetOperandClass - This is the target's operand class, like X86Operand.
|
|
std::string TargetOperandClass = Target.getName() + "Operand";
|
|
|
|
for (std::vector<InstructionInfo*>::const_iterator it = Infos.begin(),
|
|
ie = Infos.end(); it != ie; ++it) {
|
|
InstructionInfo &II = **it;
|
|
|
|
// Order the (class) operands by the order to convert them into an MCInst.
|
|
SmallVector<std::pair<unsigned, unsigned>, 4> MIOperandList;
|
|
for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) {
|
|
InstructionInfo::Operand &Op = II.Operands[i];
|
|
if (Op.OperandInfo)
|
|
MIOperandList.push_back(std::make_pair(Op.OperandInfo->MIOperandNo, i));
|
|
}
|
|
|
|
// Find any tied operands.
|
|
SmallVector<std::pair<unsigned, unsigned>, 4> TiedOperands;
|
|
for (unsigned i = 0, e = II.Instr->OperandList.size(); i != e; ++i) {
|
|
const CodeGenInstruction::OperandInfo &OpInfo = II.Instr->OperandList[i];
|
|
for (unsigned j = 0, e = OpInfo.Constraints.size(); j != e; ++j) {
|
|
const CodeGenInstruction::ConstraintInfo &CI = OpInfo.Constraints[j];
|
|
if (CI.isTied())
|
|
TiedOperands.push_back(std::make_pair(OpInfo.MIOperandNo + j,
|
|
CI.getTiedOperand()));
|
|
}
|
|
}
|
|
|
|
std::sort(MIOperandList.begin(), MIOperandList.end());
|
|
|
|
// Compute the total number of operands.
|
|
unsigned NumMIOperands = 0;
|
|
for (unsigned i = 0, e = II.Instr->OperandList.size(); i != e; ++i) {
|
|
const CodeGenInstruction::OperandInfo &OI = II.Instr->OperandList[i];
|
|
NumMIOperands = std::max(NumMIOperands,
|
|
OI.MIOperandNo + OI.MINumOperands);
|
|
}
|
|
|
|
// Build the conversion function signature.
|
|
std::string Signature = "Convert";
|
|
unsigned CurIndex = 0;
|
|
for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) {
|
|
InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second];
|
|
assert(CurIndex <= Op.OperandInfo->MIOperandNo &&
|
|
"Duplicate match for instruction operand!");
|
|
|
|
// Skip operands which weren't matched by anything, this occurs when the
|
|
// .td file encodes "implicit" operands as explicit ones.
|
|
//
|
|
// FIXME: This should be removed from the MCInst structure.
|
|
for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) {
|
|
std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
|
|
CurIndex);
|
|
if (!Tie)
|
|
Signature += "__Imp";
|
|
else
|
|
Signature += "__Tie" + utostr(Tie->second);
|
|
}
|
|
|
|
Signature += "__";
|
|
|
|
// Registers are always converted the same, don't duplicate the conversion
|
|
// function based on them.
|
|
//
|
|
// FIXME: We could generalize this based on the render method, if it
|
|
// mattered.
|
|
if (Op.Class->isRegisterClass())
|
|
Signature += "Reg";
|
|
else
|
|
Signature += Op.Class->ClassName;
|
|
Signature += utostr(Op.OperandInfo->MINumOperands);
|
|
Signature += "_" + utostr(MIOperandList[i].second);
|
|
|
|
CurIndex += Op.OperandInfo->MINumOperands;
|
|
}
|
|
|
|
// Add any trailing implicit operands.
|
|
for (; CurIndex != NumMIOperands; ++CurIndex) {
|
|
std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
|
|
CurIndex);
|
|
if (!Tie)
|
|
Signature += "__Imp";
|
|
else
|
|
Signature += "__Tie" + utostr(Tie->second);
|
|
}
|
|
|
|
II.ConversionFnKind = Signature;
|
|
|
|
// Check if we have already generated this signature.
|
|
if (!GeneratedFns.insert(Signature).second)
|
|
continue;
|
|
|
|
// If not, emit it now.
|
|
|
|
// Add to the enum list.
|
|
OS << " " << Signature << ",\n";
|
|
|
|
// And to the convert function.
|
|
CvtOS << " case " << Signature << ":\n";
|
|
CurIndex = 0;
|
|
for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) {
|
|
InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second];
|
|
|
|
// Add the implicit operands.
|
|
for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) {
|
|
// See if this is a tied operand.
|
|
std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
|
|
CurIndex);
|
|
|
|
if (!Tie) {
|
|
// If not, this is some implicit operand. Just assume it is a register
|
|
// for now.
|
|
CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
|
|
} else {
|
|
// Copy the tied operand.
|
|
assert(Tie->first>Tie->second && "Tied operand preceeds its target!");
|
|
CvtOS << " Inst.addOperand(Inst.getOperand("
|
|
<< Tie->second << "));\n";
|
|
}
|
|
}
|
|
|
|
CvtOS << " ((" << TargetOperandClass << "*)Operands["
|
|
<< MIOperandList[i].second
|
|
<< "+1])->" << Op.Class->RenderMethod
|
|
<< "(Inst, " << Op.OperandInfo->MINumOperands << ");\n";
|
|
CurIndex += Op.OperandInfo->MINumOperands;
|
|
}
|
|
|
|
// And add trailing implicit operands.
|
|
for (; CurIndex != NumMIOperands; ++CurIndex) {
|
|
std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
|
|
CurIndex);
|
|
|
|
if (!Tie) {
|
|
// If not, this is some implicit operand. Just assume it is a register
|
|
// for now.
|
|
CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
|
|
} else {
|
|
// Copy the tied operand.
|
|
assert(Tie->first>Tie->second && "Tied operand preceeds its target!");
|
|
CvtOS << " Inst.addOperand(Inst.getOperand("
|
|
<< Tie->second << "));\n";
|
|
}
|
|
}
|
|
|
|
CvtOS << " return;\n";
|
|
}
|
|
|
|
// Finish the convert function.
|
|
|
|
CvtOS << " }\n";
|
|
CvtOS << "}\n\n";
|
|
|
|
// Finish the enum, and drop the convert function after it.
|
|
|
|
OS << " NumConversionVariants\n";
|
|
OS << "};\n\n";
|
|
|
|
OS << CvtOS.str();
|
|
}
|
|
|
|
/// EmitMatchClassEnumeration - Emit the enumeration for match class kinds.
|
|
static void EmitMatchClassEnumeration(CodeGenTarget &Target,
|
|
std::vector<ClassInfo*> &Infos,
|
|
raw_ostream &OS) {
|
|
OS << "namespace {\n\n";
|
|
|
|
OS << "/// MatchClassKind - The kinds of classes which participate in\n"
|
|
<< "/// instruction matching.\n";
|
|
OS << "enum MatchClassKind {\n";
|
|
OS << " InvalidMatchClass = 0,\n";
|
|
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
|
ie = Infos.end(); it != ie; ++it) {
|
|
ClassInfo &CI = **it;
|
|
OS << " " << CI.Name << ", // ";
|
|
if (CI.Kind == ClassInfo::Token) {
|
|
OS << "'" << CI.ValueName << "'\n";
|
|
} else if (CI.isRegisterClass()) {
|
|
if (!CI.ValueName.empty())
|
|
OS << "register class '" << CI.ValueName << "'\n";
|
|
else
|
|
OS << "derived register class\n";
|
|
} else {
|
|
OS << "user defined class '" << CI.ValueName << "'\n";
|
|
}
|
|
}
|
|
OS << " NumMatchClassKinds\n";
|
|
OS << "};\n\n";
|
|
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
/// EmitClassifyOperand - Emit the function to classify an operand.
|
|
static void EmitClassifyOperand(CodeGenTarget &Target,
|
|
AsmMatcherInfo &Info,
|
|
raw_ostream &OS) {
|
|
OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
|
|
<< " " << Target.getName() << "Operand &Operand = *("
|
|
<< Target.getName() << "Operand*)GOp;\n";
|
|
|
|
// Classify tokens.
|
|
OS << " if (Operand.isToken())\n";
|
|
OS << " return MatchTokenString(Operand.getToken());\n\n";
|
|
|
|
// Classify registers.
|
|
//
|
|
// FIXME: Don't hardcode isReg, getReg.
|
|
OS << " if (Operand.isReg()) {\n";
|
|
OS << " switch (Operand.getReg()) {\n";
|
|
OS << " default: return InvalidMatchClass;\n";
|
|
for (std::map<Record*, ClassInfo*>::iterator
|
|
it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
|
|
it != ie; ++it)
|
|
OS << " case " << Target.getName() << "::"
|
|
<< it->first->getName() << ": return " << it->second->Name << ";\n";
|
|
OS << " }\n";
|
|
OS << " }\n\n";
|
|
|
|
// Classify user defined operands.
|
|
for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
|
|
ie = Info.Classes.end(); it != ie; ++it) {
|
|
ClassInfo &CI = **it;
|
|
|
|
if (!CI.isUserClass())
|
|
continue;
|
|
|
|
OS << " // '" << CI.ClassName << "' class";
|
|
if (!CI.SuperClasses.empty()) {
|
|
OS << ", subclass of ";
|
|
for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
|
|
if (i) OS << ", ";
|
|
OS << "'" << CI.SuperClasses[i]->ClassName << "'";
|
|
assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
|
|
}
|
|
}
|
|
OS << "\n";
|
|
|
|
OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
|
|
|
|
// Validate subclass relationships.
|
|
if (!CI.SuperClasses.empty()) {
|
|
for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
|
|
OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
|
|
<< "() && \"Invalid class relationship!\");\n";
|
|
}
|
|
|
|
OS << " return " << CI.Name << ";\n";
|
|
OS << " }\n\n";
|
|
}
|
|
OS << " return InvalidMatchClass;\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
/// EmitIsSubclass - Emit the subclass predicate function.
|
|
static void EmitIsSubclass(CodeGenTarget &Target,
|
|
std::vector<ClassInfo*> &Infos,
|
|
raw_ostream &OS) {
|
|
OS << "/// IsSubclass - Compute whether \\arg A is a subclass of \\arg B.\n";
|
|
OS << "static bool IsSubclass(MatchClassKind A, MatchClassKind B) {\n";
|
|
OS << " if (A == B)\n";
|
|
OS << " return true;\n\n";
|
|
|
|
OS << " switch (A) {\n";
|
|
OS << " default:\n";
|
|
OS << " return false;\n";
|
|
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
|
ie = Infos.end(); it != ie; ++it) {
|
|
ClassInfo &A = **it;
|
|
|
|
if (A.Kind != ClassInfo::Token) {
|
|
std::vector<StringRef> SuperClasses;
|
|
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
|
ie = Infos.end(); it != ie; ++it) {
|
|
ClassInfo &B = **it;
|
|
|
|
if (&A != &B && A.isSubsetOf(B))
|
|
SuperClasses.push_back(B.Name);
|
|
}
|
|
|
|
if (SuperClasses.empty())
|
|
continue;
|
|
|
|
OS << "\n case " << A.Name << ":\n";
|
|
|
|
if (SuperClasses.size() == 1) {
|
|
OS << " return B == " << SuperClasses.back() << ";\n";
|
|
continue;
|
|
}
|
|
|
|
OS << " switch (B) {\n";
|
|
OS << " default: return false;\n";
|
|
for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
|
|
OS << " case " << SuperClasses[i] << ": return true;\n";
|
|
OS << " }\n";
|
|
}
|
|
}
|
|
OS << " }\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
|
|
|
|
/// EmitMatchTokenString - Emit the function to match a token string to the
|
|
/// appropriate match class value.
|
|
static void EmitMatchTokenString(CodeGenTarget &Target,
|
|
std::vector<ClassInfo*> &Infos,
|
|
raw_ostream &OS) {
|
|
// Construct the match list.
|
|
std::vector<StringMatcher::StringPair> Matches;
|
|
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
|
ie = Infos.end(); it != ie; ++it) {
|
|
ClassInfo &CI = **it;
|
|
|
|
if (CI.Kind == ClassInfo::Token)
|
|
Matches.push_back(StringMatcher::StringPair(CI.ValueName,
|
|
"return " + CI.Name + ";"));
|
|
}
|
|
|
|
OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n";
|
|
|
|
StringMatcher("Name", Matches, OS).Emit();
|
|
|
|
OS << " return InvalidMatchClass;\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
/// EmitMatchRegisterName - Emit the function to match a string to the target
|
|
/// specific register enum.
|
|
static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
|
|
raw_ostream &OS) {
|
|
// Construct the match list.
|
|
std::vector<StringMatcher::StringPair> Matches;
|
|
for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
|
|
const CodeGenRegister &Reg = Target.getRegisters()[i];
|
|
if (Reg.TheDef->getValueAsString("AsmName").empty())
|
|
continue;
|
|
|
|
Matches.push_back(StringMatcher::StringPair(
|
|
Reg.TheDef->getValueAsString("AsmName"),
|
|
"return " + utostr(i + 1) + ";"));
|
|
}
|
|
|
|
OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
|
|
|
|
StringMatcher("Name", Matches, OS).Emit();
|
|
|
|
OS << " return 0;\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
|
|
/// definitions.
|
|
static void EmitSubtargetFeatureFlagEnumeration(CodeGenTarget &Target,
|
|
AsmMatcherInfo &Info,
|
|
raw_ostream &OS) {
|
|
OS << "// Flags for subtarget features that participate in "
|
|
<< "instruction matching.\n";
|
|
OS << "enum SubtargetFeatureFlag {\n";
|
|
for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
|
|
it = Info.SubtargetFeatures.begin(),
|
|
ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
|
|
SubtargetFeatureInfo &SFI = *it->second;
|
|
OS << " " << SFI.EnumName << " = (1 << " << SFI.Index << "),\n";
|
|
}
|
|
OS << " Feature_None = 0\n";
|
|
OS << "};\n\n";
|
|
}
|
|
|
|
/// EmitComputeAvailableFeatures - Emit the function to compute the list of
|
|
/// available features given a subtarget.
|
|
static void EmitComputeAvailableFeatures(CodeGenTarget &Target,
|
|
AsmMatcherInfo &Info,
|
|
raw_ostream &OS) {
|
|
std::string ClassName =
|
|
Info.AsmParser->getValueAsString("AsmParserClassName");
|
|
|
|
OS << "unsigned " << Target.getName() << ClassName << "::\n"
|
|
<< "ComputeAvailableFeatures(const " << Target.getName()
|
|
<< "Subtarget *Subtarget) const {\n";
|
|
OS << " unsigned Features = 0;\n";
|
|
for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
|
|
it = Info.SubtargetFeatures.begin(),
|
|
ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
|
|
SubtargetFeatureInfo &SFI = *it->second;
|
|
OS << " if (" << SFI.TheDef->getValueAsString("CondString")
|
|
<< ")\n";
|
|
OS << " Features |= " << SFI.EnumName << ";\n";
|
|
}
|
|
OS << " return Features;\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
void AsmMatcherEmitter::run(raw_ostream &OS) {
|
|
CodeGenTarget Target;
|
|
Record *AsmParser = Target.getAsmParser();
|
|
std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
|
|
|
|
// Compute the information on the instructions to match.
|
|
AsmMatcherInfo Info(AsmParser);
|
|
Info.BuildInfo(Target);
|
|
|
|
// Sort the instruction table using the partial order on classes. We use
|
|
// stable_sort to ensure that ambiguous instructions are still
|
|
// deterministically ordered.
|
|
std::stable_sort(Info.Instructions.begin(), Info.Instructions.end(),
|
|
less_ptr<InstructionInfo>());
|
|
|
|
DEBUG_WITH_TYPE("instruction_info", {
|
|
for (std::vector<InstructionInfo*>::iterator
|
|
it = Info.Instructions.begin(), ie = Info.Instructions.end();
|
|
it != ie; ++it)
|
|
(*it)->dump();
|
|
});
|
|
|
|
// Check for ambiguous instructions.
|
|
DEBUG_WITH_TYPE("ambiguous_instrs", {
|
|
unsigned NumAmbiguous = 0;
|
|
for (unsigned i = 0, e = Info.Instructions.size(); i != e; ++i) {
|
|
for (unsigned j = i + 1; j != e; ++j) {
|
|
InstructionInfo &A = *Info.Instructions[i];
|
|
InstructionInfo &B = *Info.Instructions[j];
|
|
|
|
if (A.CouldMatchAmiguouslyWith(B)) {
|
|
errs() << "warning: ambiguous instruction match:\n";
|
|
A.dump();
|
|
errs() << "\nis incomparable with:\n";
|
|
B.dump();
|
|
errs() << "\n\n";
|
|
++NumAmbiguous;
|
|
}
|
|
}
|
|
}
|
|
if (NumAmbiguous)
|
|
errs() << "warning: " << NumAmbiguous
|
|
<< " ambiguous instructions!\n";
|
|
});
|
|
|
|
// Write the output.
|
|
|
|
EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
|
|
|
|
// Information for the class declaration.
|
|
OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
|
|
OS << "#undef GET_ASSEMBLER_HEADER\n";
|
|
OS << " // This should be included into the middle of the declaration of \n";
|
|
OS << " // your subclasses implementation of TargetAsmParser.\n";
|
|
OS << " unsigned ComputeAvailableFeatures(const " <<
|
|
Target.getName() << "Subtarget *Subtarget) const;\n";
|
|
OS << " enum MatchResultTy {\n";
|
|
OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n";
|
|
OS << " Match_MissingFeature\n";
|
|
OS << " };\n";
|
|
OS << " MatchResultTy MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
|
|
<< " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
|
|
OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
|
|
|
|
|
|
|
|
|
|
OS << "\n#ifdef GET_REGISTER_MATCHER\n";
|
|
OS << "#undef GET_REGISTER_MATCHER\n\n";
|
|
|
|
// Emit the subtarget feature enumeration.
|
|
EmitSubtargetFeatureFlagEnumeration(Target, Info, OS);
|
|
|
|
// Emit the function to match a register name to number.
|
|
EmitMatchRegisterName(Target, AsmParser, OS);
|
|
|
|
OS << "#endif // GET_REGISTER_MATCHER\n\n";
|
|
|
|
|
|
OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
|
|
OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
|
|
|
|
// Generate the unified function to convert operands into an MCInst.
|
|
EmitConvertToMCInst(Target, Info.Instructions, OS);
|
|
|
|
// Emit the enumeration for classes which participate in matching.
|
|
EmitMatchClassEnumeration(Target, Info.Classes, OS);
|
|
|
|
// Emit the routine to match token strings to their match class.
|
|
EmitMatchTokenString(Target, Info.Classes, OS);
|
|
|
|
// Emit the routine to classify an operand.
|
|
EmitClassifyOperand(Target, Info, OS);
|
|
|
|
// Emit the subclass predicate routine.
|
|
EmitIsSubclass(Target, Info.Classes, OS);
|
|
|
|
// Emit the available features compute function.
|
|
EmitComputeAvailableFeatures(Target, Info, OS);
|
|
|
|
|
|
size_t MaxNumOperands = 0;
|
|
for (std::vector<InstructionInfo*>::const_iterator it =
|
|
Info.Instructions.begin(), ie = Info.Instructions.end();
|
|
it != ie; ++it)
|
|
MaxNumOperands = std::max(MaxNumOperands, (*it)->Operands.size());
|
|
|
|
|
|
// Emit the static match table; unused classes get initalized to 0 which is
|
|
// guaranteed to be InvalidMatchClass.
|
|
//
|
|
// FIXME: We can reduce the size of this table very easily. First, we change
|
|
// it so that store the kinds in separate bit-fields for each index, which
|
|
// only needs to be the max width used for classes at that index (we also need
|
|
// to reject based on this during classification). If we then make sure to
|
|
// order the match kinds appropriately (putting mnemonics last), then we
|
|
// should only end up using a few bits for each class, especially the ones
|
|
// following the mnemonic.
|
|
OS << "namespace {\n";
|
|
OS << " struct MatchEntry {\n";
|
|
OS << " unsigned Opcode;\n";
|
|
OS << " const char *Mnemonic;\n";
|
|
OS << " ConversionKind ConvertFn;\n";
|
|
OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
|
|
OS << " unsigned RequiredFeatures;\n";
|
|
OS << " };\n\n";
|
|
|
|
OS << "// Predicate for searching for an opcode.\n";
|
|
OS << " struct LessOpcode {\n";
|
|
OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
|
|
OS << " return StringRef(LHS.Mnemonic) < RHS;\n";
|
|
OS << " }\n";
|
|
OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
|
|
OS << " return LHS < StringRef(RHS.Mnemonic);\n";
|
|
OS << " }\n";
|
|
OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
|
|
OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
|
|
OS << " }\n";
|
|
OS << " };\n";
|
|
|
|
OS << "} // end anonymous namespace.\n\n";
|
|
|
|
OS << "static const MatchEntry MatchTable["
|
|
<< Info.Instructions.size() << "] = {\n";
|
|
|
|
for (std::vector<InstructionInfo*>::const_iterator it =
|
|
Info.Instructions.begin(), ie = Info.Instructions.end();
|
|
it != ie; ++it) {
|
|
InstructionInfo &II = **it;
|
|
|
|
OS << " { " << Target.getName() << "::" << II.InstrName
|
|
<< ", \"" << II.Tokens[0] << "\""
|
|
<< ", " << II.ConversionFnKind << ", { ";
|
|
for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) {
|
|
InstructionInfo::Operand &Op = II.Operands[i];
|
|
|
|
if (i) OS << ", ";
|
|
OS << Op.Class->Name;
|
|
}
|
|
OS << " }, ";
|
|
|
|
// Write the required features mask.
|
|
if (!II.RequiredFeatures.empty()) {
|
|
for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
|
|
if (i) OS << "|";
|
|
OS << II.RequiredFeatures[i]->EnumName;
|
|
}
|
|
} else
|
|
OS << "0";
|
|
|
|
OS << "},\n";
|
|
}
|
|
|
|
OS << "};\n\n";
|
|
|
|
// Finally, build the match function.
|
|
OS << Target.getName() << ClassName << "::MatchResultTy "
|
|
<< Target.getName() << ClassName << "::\n"
|
|
<< "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>"
|
|
<< " &Operands,\n";
|
|
OS << " MCInst &Inst, unsigned &ErrorInfo) {\n";
|
|
|
|
// Emit code to get the available features.
|
|
OS << " // Get the current feature set.\n";
|
|
OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
|
|
|
|
// Emit code to compute the class list for this operand vector.
|
|
OS << " // Eliminate obvious mismatches.\n";
|
|
OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
|
|
OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
|
|
OS << " return Match_InvalidOperand;\n";
|
|
OS << " }\n\n";
|
|
|
|
OS << " // Compute the class list for this operand vector.\n";
|
|
OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
|
|
OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n";
|
|
OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n";
|
|
|
|
OS << " // Check for invalid operands before matching.\n";
|
|
OS << " if (Classes[i-1] == InvalidMatchClass) {\n";
|
|
OS << " ErrorInfo = i;\n";
|
|
OS << " return Match_InvalidOperand;\n";
|
|
OS << " }\n";
|
|
OS << " }\n\n";
|
|
|
|
OS << " // Mark unused classes.\n";
|
|
OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; "
|
|
<< "i != e; ++i)\n";
|
|
OS << " Classes[i] = InvalidMatchClass;\n\n";
|
|
|
|
OS << " // Get the instruction mnemonic, which is the first token.\n";
|
|
OS << " StringRef Mnemonic = ((" << Target.getName()
|
|
<< "Operand*)Operands[0])->getToken();\n\n";
|
|
|
|
OS << " // Some state to try to produce better error messages.\n";
|
|
OS << " bool HadMatchOtherThanFeatures = false;\n\n";
|
|
OS << " // Set ErrorInfo to the operand that mismatches if it is \n";
|
|
OS << " // wrong for all instances of the instruction.\n";
|
|
OS << " ErrorInfo = ~0U;\n";
|
|
|
|
// Emit code to search the table.
|
|
OS << " // Search the table.\n";
|
|
OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
|
|
OS << " std::equal_range(MatchTable, MatchTable+"
|
|
<< Info.Instructions.size() << ", Mnemonic, LessOpcode());\n\n";
|
|
|
|
OS << " // Return a more specific error code if no mnemonics match.\n";
|
|
OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
|
|
OS << " return Match_MnemonicFail;\n\n";
|
|
|
|
OS << " for (const MatchEntry *it = MnemonicRange.first, "
|
|
<< "*ie = MnemonicRange.second;\n";
|
|
OS << " it != ie; ++it) {\n";
|
|
|
|
OS << " // equal_range guarantees that instruction mnemonic matches.\n";
|
|
OS << " assert(Mnemonic == it->Mnemonic);\n";
|
|
|
|
// Emit check that the subclasses match.
|
|
OS << " bool OperandsValid = true;\n";
|
|
OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
|
|
OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n";
|
|
OS << " continue;\n";
|
|
OS << " // If this operand is broken for all of the instances of this\n";
|
|
OS << " // mnemonic, keep track of it so we can report loc info.\n";
|
|
OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n";
|
|
OS << " ErrorInfo = i+1;\n";
|
|
OS << " else\n";
|
|
OS << " ErrorInfo = ~0U;";
|
|
OS << " // Otherwise, just reject this instance of the mnemonic.\n";
|
|
OS << " OperandsValid = false;\n";
|
|
OS << " break;\n";
|
|
OS << " }\n\n";
|
|
|
|
OS << " if (!OperandsValid) continue;\n";
|
|
|
|
// Emit check that the required features are available.
|
|
OS << " if ((AvailableFeatures & it->RequiredFeatures) "
|
|
<< "!= it->RequiredFeatures) {\n";
|
|
OS << " HadMatchOtherThanFeatures = true;\n";
|
|
OS << " continue;\n";
|
|
OS << " }\n";
|
|
|
|
OS << "\n";
|
|
OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
|
|
|
|
// Call the post-processing function, if used.
|
|
std::string InsnCleanupFn =
|
|
AsmParser->getValueAsString("AsmParserInstCleanup");
|
|
if (!InsnCleanupFn.empty())
|
|
OS << " " << InsnCleanupFn << "(Inst);\n";
|
|
|
|
OS << " return Match_Success;\n";
|
|
OS << " }\n\n";
|
|
|
|
OS << " // Okay, we had no match. Try to return a useful error code.\n";
|
|
OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
|
|
OS << " return Match_InvalidOperand;\n";
|
|
OS << "}\n\n";
|
|
|
|
OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
|
|
}
|