mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
8bf61e8c2a
issue is operand promotion for setcc/select... but looks like the fundamental stuff is implemented for CellSPU. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51884 91177308-0d34-0410-b5e6-96231b3b80d8
94 lines
2.4 KiB
LLVM
94 lines
2.4 KiB
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep lqa %t1.s | count 13
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; RUN: grep il %t1.s | count 22
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; RUN: grep shufb %t1.s | count 13
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; RUN: grep 65520 %t1.s | count 1
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; RUN: grep 43981 %t1.s | count 1
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; RUN: grep 13702 %t1.s | count 1
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; RUN: grep 28225 %t1.s | count 1
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; RUN: grep 30720 %t1.s | count 1
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; RUN: grep 3233857728 %t1.s | count 8
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; RUN: grep 2155905152 %t1.s | count 6
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; RUN: grep 66051 %t1.s | count 7
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; RUN: grep 471670303 %t1.s | count 11
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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; 1311768467750121234 => 0x 12345678 abcdef12 (4660,22136/43981,61202)
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; 18446744073709551591 => 0x ffffffff ffffffe7 (-25)
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; 18446744073708516742 => 0x ffffffff fff03586 (-1034874)
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; 5308431 => 0x 00000000 0051000F
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; 9223372038704560128 => 0x 80000000 6e417800
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define i64 @i64_const_1() {
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ret i64 1311768467750121234 ;; Constant pool spill
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}
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define i64 @i64_const_2() {
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ret i64 18446744073709551591 ;; IL/SHUFB
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}
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define i64 @i64_const_3() {
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ret i64 18446744073708516742 ;; IHLU/IOHL/SHUFB
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}
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define i64 @i64_const_4() {
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ret i64 5308431 ;; ILHU/IOHL/SHUFB
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}
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define i64 @i64_const_5() {
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ret i64 511 ;; IL/SHUFB
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}
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define i64 @i64_const_6() {
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ret i64 -512 ;; IL/SHUFB
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}
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define i64 @i64_const_7() {
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ret i64 9223372038704560128 ;; IHLU/IOHL/SHUFB
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}
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define i64 @i64_const_8() {
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ret i64 0 ;; IL
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}
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define i64 @i64_const_9() {
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ret i64 -1 ;; IL
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}
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define i64 @i64_const_10() {
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ret i64 281470681808895 ;; IL 65535
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}
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; 0x4005bf0a8b145769 ->
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; (ILHU 0x4005 [16389]/IOHL 0xbf0a [48906])
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; (ILHU 0x8b14 [35604]/IOHL 0x5769 [22377])
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define double @f64_const_1() {
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ret double 0x4005bf0a8b145769 ;; ILHU/IOHL via pattern
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}
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define double @f64_const_2() {
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ret double 0x0010000000000000
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}
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define double @f64_const_3() {
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ret double 0x7fefffffffffffff
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}
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define double @f64_const_4() {
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ret double 0x400921fb54442d18
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}
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define double @f64_const_5() {
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ret double 0xbff6a09e667f3bcd ;; ILHU/IOHL via pattern
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}
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define double @f64_const_6() {
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ret double 0x3ff6a09e667f3bcd
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}
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define double @f64_const_7() {
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ret double 0.000000e+00
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}
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