Tom Stellard ac1a45e511 AMDGPU/SI: Add hsa code object directives ...

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10757

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240831 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-26 21:15:07 +00:00

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AArch64

[AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch also adds a function to calculate the cost of interleaved memory accesses.

2015-06-26 02:32:07 +00:00

AMDGPU

AMDGPU/SI: Add hsa code object directives

2015-06-26 21:15:07 +00:00

ARM

[ARM] Cortex-R5 is not VFPOnlySP

2015-06-26 17:42:37 +00:00

BPF

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CPP

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Generic

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Hexagon

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Inputs

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Mips

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MIR

MIR Serialization: Serialize machine basic block operands.

2015-06-26 16:46:11 +00:00

MSP430

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NVPTX

Add NVPTXPeephole pass to reduce unnecessary address cast

2015-06-24 20:20:16 +00:00

PowerPC

Add missing builtins to the PPC back end for ABI compliance (vol. 1)

2015-06-26 19:26:53 +00:00

SPARC

Revert r240302 ("Bring r240130 back.").

2015-06-23 11:31:32 +00:00

SystemZ

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Thumb

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Thumb2

ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually test for it

2015-06-24 20:03:27 +00:00

WinEH

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X86

Revert "Revert r240762 "[X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant""

2015-06-26 18:55:48 +00:00

XCore

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