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mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-20 11:32:33 +00:00
Jim Grosbach ac915b48d8 TableGen: Allow conditional instruction pattern in multiclass.
Define a 'null_frag' SDPatternOperator node, which if referenced in an
instruction Pattern, results in the pattern being collapsed to be as-if
'[]' had been specified instead. This allows supporting a multiclass
definition where some instaniations have ISel patterns associated and
others do not.

For example,
multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> {
  def _x : myI<(outs rc:), (ins rc:), []>;
  def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>;
}

defm foo : myMulti<GRa, not>;
defm bar : myMulti<GRb>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 00:47:06 +00:00
2012-07-12 13:18:13 +00:00
2012-05-02 21:25:32 +00:00
2012-06-19 23:47:58 +00:00
2012-07-11 17:34:12 +00:00

Low Level Virtual Machine (LLVM)
================================

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LLVM backend for 6502
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