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https://github.com/c64scene-ar/llvm-6502.git
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acc068e873
X86ISelLowering C++ code. Because this is lowered via an xor wrapped around a bsr, we want the dagcombine which runs after isel lowering to have a chance to clean things up. In particular, it is very common to see code which looks like: (sizeof(x)*8 - 1) ^ __builtin_clz(x) Which is trying to compute the most significant bit of 'x'. That's actually the value computed directly by the 'bsr' instruction, but if we match it too late, we'll get completely redundant xor instructions. The more naive code for the above (subtracting rather than using an xor) still isn't handled correctly due to the dagcombine getting confused. Also, while here fix an issue spotted by inspection: we should have been expanding the zero-undef variants to the normal variants when there is an 'lzcnt' instruction. Do so, and test for this. We don't want to generate unnecessary 'bsr' instructions. These two changes fix some regressions in encoding and decoding benchmarks. However, there is still a *lot* to be improve on in this type of code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147244 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
2.0 KiB
LLVM
91 lines
2.0 KiB
LLVM
; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
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define i32 @t1(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true )
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ret i32 %tmp
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; CHECK: t1:
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; CHECK: bsrl
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; CHECK-NOT: cmov
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; CHECK: xorl $31,
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; CHECK: ret
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}
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declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
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define i32 @t2(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true )
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ret i32 %tmp
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; CHECK: t2:
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; CHECK: bsfl
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; CHECK-NOT: cmov
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; CHECK: ret
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}
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declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
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define i16 @t3(i16 %x, i16 %y) nounwind {
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entry:
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%tmp1 = add i16 %x, %y
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%tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true ) ; <i16> [#uses=1]
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ret i16 %tmp2
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; CHECK: t3:
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; CHECK: bsrw
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; CHECK-NOT: cmov
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; CHECK: xorl $15,
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; CHECK: ret
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}
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declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone
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define i32 @t4(i32 %n) nounwind {
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entry:
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; Generate a cmov to handle zero inputs when necessary.
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; CHECK: t4:
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; CHECK: bsrl
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; CHECK: cmov
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; CHECK: xorl $31,
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; CHECK: ret
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%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %n, i1 false)
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ret i32 %tmp1
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}
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define i32 @t5(i32 %n) nounwind {
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entry:
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; Don't generate the cmovne when the source is known non-zero (and bsr would
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; not set ZF).
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; rdar://9490949
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; CHECK: t5:
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; CHECK: bsrl
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; CHECK-NOT: cmov
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; CHECK: xorl $31,
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; CHECK: ret
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%or = or i32 %n, 1
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%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or, i1 false)
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ret i32 %tmp1
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}
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define i32 @t6(i32 %n) nounwind {
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entry:
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; Don't generate any xors when a 'ctlz' intrinsic is actually used to compute
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; the most significant bit, which is what 'bsr' does natively.
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; CHECK: t6:
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; CHECK: bsrl
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; CHECK-NOT: xorl
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; CHECK: ret
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%ctlz = tail call i32 @llvm.ctlz.i32(i32 %n, i1 true)
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%bsr = xor i32 %ctlz, 31
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ret i32 %bsr
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}
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define i32 @t7(i32 %n) nounwind {
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entry:
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; Same as t6, but ensure this happens even when there is a potential zero.
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; CHECK: t7:
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; CHECK: bsrl
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; CHECK-NOT: xorl
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; CHECK: ret
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%ctlz = tail call i32 @llvm.ctlz.i32(i32 %n, i1 false)
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%bsr = xor i32 %ctlz, 31
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ret i32 %bsr
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}
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