mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-05-29 07:39:27 +00:00
adf55a5a57
The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds LLVM support to enable those builtins. In partciular, the patch: - adds the transactional-execution and processor-assist facilities - adds MC support for all instructions provided by those facilities - adds LLVM intrinsics for those instructions and hooks them up for CodeGen - adds CodeGen support to optimize CC return value checking Since this is first use of target-specific intrinsics on the platform, the patch creates the include/llvm/IR/IntrinsicsSystemZ.td file and hooks it up in Intrinsics.td. I've also changed Triple::getArchTypePrefix to return "s390" instead of "systemz", since the naming convention for GCC intrinsics uses "s390" on the platform, and it neemed more straight- forward to use the same convention for LLVM IR intrinsics. An associated clang patch makes the intrinsics (and command line switches) available at the source-language level. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html Index: llvm-head/lib/Target/SystemZ/SystemZOperators.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZOperators.td +++ llvm-head/lib/Target/SystemZ/SystemZOperators.td @@ -79,6 +79,9 @@ def SDT_ZI32Intrinsic : SDTypeProf def SDT_ZPrefetch : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>; +def SDT_ZTBegin : SDTypeProfile<0, 2, + [SDTCisPtrTy<0>, + SDTCisVT<1, i32>]>; //===----------------------------------------------------------------------===// // Node definitions @@ -180,6 +183,15 @@ def z_prefetch : SDNode<"System [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin, + [SDNPHasChain, SDNPOutGlue, SDNPMayStore, + SDNPSideEffect]>; +def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin, + [SDNPHasChain, SDNPOutGlue, SDNPMayStore, + SDNPSideEffect]>; +def z_tend : SDNode<"SystemZISD::TEND", SDTNone, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; + //===----------------------------------------------------------------------===// // Pattern fragments //===----------------------------------------------------------------------===// Index: llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZInstrFormats.td +++ llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td @@ -473,6 +473,17 @@ class InstSS<bits<8> op, dag outs, dag i let Inst{15-0} = BD2; } +class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<4, outs, ins, asmstr, pattern> { + field bits<32> Inst; + field bits<32> SoftFail = 0; + + bits<16> BD2; + + let Inst{31-16} = op; + let Inst{15-0} = BD2; +} + //===----------------------------------------------------------------------===// // Instruction definitions with semantics //===----------------------------------------------------------------------===// Index: llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZInstrInfo.td +++ llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1362,6 +1362,60 @@ let Defs = [CC] in { } //===----------------------------------------------------------------------===// +// Transactional execution +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureTransactionalExecution] in { + // Transaction Begin + let hasSideEffects = 1, mayStore = 1, + usesCustomInserter = 1, Defs = [CC] in { + def TBEGIN : InstSIL<0xE560, + (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), + "tbegin\t$BD1, $I2", + [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>; + def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), + [(z_tbegin_nofloat bdaddr12only:$BD1, + imm32zx16:$I2)]>; + def TBEGINC : InstSIL<0xE561, + (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), + "tbeginc\t$BD1, $I2", + [(int_s390_tbeginc bdaddr12only:$BD1, + imm32zx16:$I2)]>; + } + + // Transaction End + let hasSideEffects = 1, Defs = [CC], BD2 = 0 in + def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>; + + // Transaction Abort + let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in + def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2), + "tabort\t$BD2", + [(int_s390_tabort bdaddr12only:$BD2)]>; + + // Nontransactional Store + let hasSideEffects = 1 in + def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; + + // Extract Transaction Nesting Depth + let hasSideEffects = 1 in + def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>; +} + +//===----------------------------------------------------------------------===// +// Processor assist +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureProcessorAssist] in { + let hasSideEffects = 1, R4 = 0 in + def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3), + "ppa\t$R1, $R2, $R3", []>; + def : Pat<(int_s390_ppa_txassist GR32:$src), + (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), + 0, 1)>; +} + +//===----------------------------------------------------------------------===// // Miscellaneous Instructions. //===----------------------------------------------------------------------===// Index: llvm-head/lib/Target/SystemZ/SystemZProcessors.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZProcessors.td +++ llvm-head/lib/Target/SystemZ/SystemZProcessors.td @@ -60,6 +60,16 @@ def FeatureMiscellaneousExtensions : Sys "Assume that the miscellaneous-extensions facility is installed" >; +def FeatureTransactionalExecution : SystemZFeature< + "transactional-execution", "TransactionalExecution", + "Assume that the transactional-execution facility is installed" +>; + +def FeatureProcessorAssist : SystemZFeature< + "processor-assist", "ProcessorAssist", + "Assume that the processor-assist facility is installed" +>; + def : Processor<"generic", NoItineraries, []>; def : Processor<"z10", NoItineraries, []>; def : Processor<"z196", NoItineraries, @@ -70,4 +80,5 @@ def : Processor<"zEC12", NoItineraries, [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord, FeatureFPExtension, FeaturePopulationCount, FeatureFastSerialization, FeatureInterlockedAccess1, - FeatureMiscellaneousExtensions]>; + FeatureMiscellaneousExtensions, + FeatureTransactionalExecution, FeatureProcessorAssist]>; Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.cpp +++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -40,6 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false), HasPopulationCount(false), HasFastSerialization(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), + HasTransactionalExecution(false), HasProcessorAssist(false), TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {} Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.h =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.h +++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.h @@ -42,6 +42,8 @@ protected: bool HasFastSerialization; bool HasInterlockedAccess1; bool HasMiscellaneousExtensions; + bool HasTransactionalExecution; + bool HasProcessorAssist; private: Triple TargetTriple; @@ -102,6 +104,12 @@ public: return HasMiscellaneousExtensions; } + // Return true if the target has the transactional-execution facility. + bool hasTransactionalExecution() const { return HasTransactionalExecution; } + + // Return true if the target has the processor-assist facility. + bool hasProcessorAssist() const { return HasProcessorAssist; } + // Return true if GV can be accessed using LARL for reloc model RM // and code model CM. bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM, Index: llvm-head/lib/Support/Triple.cpp =================================================================== --- llvm-head.orig/lib/Support/Triple.cpp +++ llvm-head/lib/Support/Triple.cpp @@ -92,7 +92,7 @@ const char *Triple::getArchTypePrefix(Ar case sparcv9: case sparc: return "sparc"; - case systemz: return "systemz"; + case systemz: return "s390"; case x86: case x86_64: return "x86"; Index: llvm-head/include/llvm/IR/Intrinsics.td =================================================================== --- llvm-head.orig/include/llvm/IR/Intrinsics.td +++ llvm-head/include/llvm/IR/Intrinsics.td @@ -634,3 +634,4 @@ include "llvm/IR/IntrinsicsNVVM.td" include "llvm/IR/IntrinsicsMips.td" include "llvm/IR/IntrinsicsR600.td" include "llvm/IR/IntrinsicsBPF.td" +include "llvm/IR/IntrinsicsSystemZ.td" Index: llvm-head/include/llvm/IR/IntrinsicsSystemZ.td =================================================================== --- /dev/null +++ llvm-head/include/llvm/IR/IntrinsicsSystemZ.td @@ -0,0 +1,46 @@ +//===- IntrinsicsSystemZ.td - Defines SystemZ intrinsics ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines all of the SystemZ-specific intrinsics. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// +// Transactional-execution intrinsics +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "s390" in { + def int_s390_tbegin : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], + [IntrNoDuplicate]>; + + def int_s390_tbegin_nofloat : Intrinsic<[llvm_i32_ty], + [llvm_ptr_ty, llvm_i32_ty], + [IntrNoDuplicate]>; + + def int_s390_tbeginc : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], + [IntrNoDuplicate]>; + + def int_s390_tabort : Intrinsic<[], [llvm_i64_ty], + [IntrNoReturn, Throws]>; + + def int_s390_tend : GCCBuiltin<"__builtin_tend">, + Intrinsic<[llvm_i32_ty], []>; + + def int_s390_etnd : GCCBuiltin<"__builtin_tx_nesting_depth">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + + def int_s390_ntstg : Intrinsic<[], [llvm_i64_ty, llvm_ptr64_ty], + [IntrReadWriteArgMem]>; + + def int_s390_ppa_txassist : GCCBuiltin<"__builtin_tx_assist">, + Intrinsic<[], [llvm_i32_ty]>; +} + Index: llvm-head/lib/Target/SystemZ/SystemZ.h =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZ.h +++ llvm-head/lib/Target/SystemZ/SystemZ.h @@ -68,6 +68,18 @@ const unsigned CCMASK_TM_MSB_0 = C const unsigned CCMASK_TM_MSB_1 = CCMASK_2 | CCMASK_3; const unsigned CCMASK_TM = CCMASK_ANY; +// Condition-code mask assignments for TRANSACTION_BEGIN. +const unsigned CCMASK_TBEGIN_STARTED = CCMASK_0; +const unsigned CCMASK_TBEGIN_INDETERMINATE = CCMASK_1; +const unsigned CCMASK_TBEGIN_TRANSIENT = CCMASK_2; +const unsigned CCMASK_TBEGIN_PERSISTENT = CCMASK_3; +const unsigned CCMASK_TBEGIN = CCMASK_ANY; + +// Condition-code mask assignments for TRANSACTION_END. +const unsigned CCMASK_TEND_TX = CCMASK_0; +const unsigned CCMASK_TEND_NOTX = CCMASK_2; +const unsigned CCMASK_TEND = CCMASK_TEND_TX | CCMASK_TEND_NOTX; + // The position of the low CC bit in an IPM result. const unsigned IPM_CC = 28; Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.h =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.h +++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.h @@ -146,6 +146,15 @@ enum { // Perform a serialization operation. (BCR 15,0 or BCR 14,0.) SERIALIZE, + // Transaction begin. The first operand is the chain, the second + // the TDB pointer, and the third the immediate control field. + // Returns chain and glue. + TBEGIN, + TBEGIN_NOFLOAT, + + // Transaction end. Just the chain operand. Returns chain and glue. + TEND, + // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or // ATOMIC_LOAD_<op>. // @@ -318,6 +327,7 @@ private: SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; // If the last instruction before MBBI in MBB was some form of COMPARE, // try to replace it with a COMPARE AND BRANCH just before MBBI. @@ -355,6 +365,10 @@ private: MachineBasicBlock *emitStringWrapper(MachineInstr *MI, MachineBasicBlock *BB, unsigned Opcode) const; + MachineBasicBlock *emitTransactionBegin(MachineInstr *MI, + MachineBasicBlock *MBB, + unsigned Opcode, + bool NoFloat) const; }; } // end namespace llvm Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.cpp +++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/IR/Intrinsics.h" #include <cctype> using namespace llvm; @@ -304,6 +305,9 @@ SystemZTargetLowering::SystemZTargetLowe // Codes for which we want to perform some z-specific combinations. setTargetDAGCombine(ISD::SIGN_EXTEND); + // Handle intrinsics. + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); + // We want to use MVC in preference to even a single load/store pair. MaxStoresPerMemcpy = 0; MaxStoresPerMemcpyOptSize = 0; @@ -1031,6 +1035,53 @@ prepareVolatileOrAtomicLoad(SDValue Chai return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain); } +// Return true if Op is an intrinsic node with chain that returns the CC value +// as its only (other) argument. Provide the associated SystemZISD opcode and +// the mask of valid CC values if so. +static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode, + unsigned &CCValid) { + unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); + switch (Id) { + case Intrinsic::s390_tbegin: + Opcode = SystemZISD::TBEGIN; + CCValid = SystemZ::CCMASK_TBEGIN; + return true; + + case Intrinsic::s390_tbegin_nofloat: + Opcode = SystemZISD::TBEGIN_NOFLOAT; + CCValid = SystemZ::CCMASK_TBEGIN; + return true; + + case Intrinsic::s390_tend: + Opcode = SystemZISD::TEND; + CCValid = SystemZ::CCMASK_TEND; + return true; + + default: + return false; + } +} + +// Emit an intrinsic with chain with a glued value instead of its CC result. +static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op, + unsigned Opcode) { + // Copy all operands except the intrinsic ID. + unsigned NumOps = Op.getNumOperands(); + SmallVector<SDValue, 6> Ops; + Ops.reserve(NumOps - 1); + Ops.push_back(Op.getOperand(0)); + for (unsigned I = 2; I < NumOps; ++I) + Ops.push_back(Op.getOperand(I)); + + assert(Op->getNumValues() == 2 && "Expected only CC result and chain"); + SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue); + SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops); + SDValue OldChain = SDValue(Op.getNode(), 1); + SDValue NewChain = SDValue(Intr.getNode(), 0); + DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain); + return Intr; +} + // CC is a comparison that will be implemented using an integer or // floating-point comparison. Return the condition code mask for // a branch on true. In the integer case, CCMASK_CMP_UO is set for @@ -1588,9 +1639,53 @@ static void adjustForTestUnderMask(Selec C.CCMask = NewCCMask; } +// Return a Comparison that tests the condition-code result of intrinsic +// node Call against constant integer CC using comparison code Cond. +// Opcode is the opcode of the SystemZISD operation for the intrinsic +// and CCValid is the set of possible condition-code results. +static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode, + SDValue Call, unsigned CCValid, uint64_t CC, + ISD::CondCode Cond) { + Comparison C(Call, SDValue()); + C.Opcode = Opcode; + C.CCValid = CCValid; + if (Cond == ISD::SETEQ) + // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3. + C.CCMask = CC < 4 ? 1 << (3 - CC) : 0; + else if (Cond == ISD::SETNE) + // ...and the inverse of that. + C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1; + else if (Cond == ISD::SETLT || Cond == ISD::SETULT) + // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3, + // always true for CC>3. + C.CCMask = CC < 4 ? -1 << (4 - CC) : -1; + else if (Cond == ISD::SETGE || Cond == ISD::SETUGE) + // ...and the inverse of that. + C.CCMask = CC < 4 ? ~(-1 << (4 - CC)) : 0; + else if (Cond == ISD::SETLE || Cond == ISD::SETULE) + // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true), + // always true for CC>3. + C.CCMask = CC < 4 ? -1 << (3 - CC) : -1; + else if (Cond == ISD::SETGT || Cond == ISD::SETUGT) + // ...and the inverse of that. + C.CCMask = CC < 4 ? ~(-1 << (3 - CC)) : 0; + else + llvm_unreachable("Unexpected integer comparison type"); + C.CCMask &= CCValid; + return C; +} + // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1. static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1, ISD::CondCode Cond) { + if (CmpOp1.getOpcode() == ISD::Constant) { + uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue(); + unsigned Opcode, CCValid; + if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN && + CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) && + isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid)) + return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond); + } Comparison C(CmpOp0, CmpOp1); C.CCMask = CCMaskForCondCode(Cond); if (C.Op0.getValueType().isFloatingPoint()) { @@ -1632,6 +1727,17 @@ static Comparison getCmp(SelectionDAG &D // Emit the comparison instruction described by C. static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) { + if (!C.Op1.getNode()) { + SDValue Op; + switch (C.Op0.getOpcode()) { + case ISD::INTRINSIC_W_CHAIN: + Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode); + break; + default: + llvm_unreachable("Invalid comparison operands"); + } + return SDValue(Op.getNode(), Op->getNumValues() - 1); + } if (C.Opcode == SystemZISD::ICMP) return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1, DAG.getConstant(C.ICmpType, MVT::i32)); @@ -1713,7 +1819,6 @@ SDValue SystemZTargetLowering::lowerSETC } SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const { - SDValue Chain = Op.getOperand(0); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); SDValue CmpOp0 = Op.getOperand(2); SDValue CmpOp1 = Op.getOperand(3); @@ -1723,7 +1828,7 @@ SDValue SystemZTargetLowering::lowerBR_C Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC)); SDValue Glue = emitCmp(DAG, DL, C); return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(), - Chain, DAG.getConstant(C.CCValid, MVT::i32), + Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32), DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue); } @@ -2561,6 +2666,30 @@ SDValue SystemZTargetLowering::lowerPREF Node->getMemoryVT(), Node->getMemOperand()); } +// Return an i32 that contains the value of CC immediately after After, +// whose final operand must be MVT::Glue. +static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) { + SDValue Glue = SDValue(After, After->getNumValues() - 1); + SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue); + return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM, + DAG.getConstant(SystemZ::IPM_CC, MVT::i32)); +} + +SDValue +SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, + SelectionDAG &DAG) const { + unsigned Opcode, CCValid; + if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) { + assert(Op->getNumValues() == 2 && "Expected only CC result and chain"); + SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode); + SDValue CC = getCCResult(DAG, Glued.getNode()); + DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC); + return SDValue(); + } + + return SDValue(); +} + SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { @@ -2634,6 +2763,8 @@ SDValue SystemZTargetLowering::LowerOper return lowerSTACKRESTORE(Op, DAG); case ISD::PREFETCH: return lowerPREFETCH(Op, DAG); + case ISD::INTRINSIC_W_CHAIN: + return lowerINTRINSIC_W_CHAIN(Op, DAG); default: llvm_unreachable("Unexpected node to lower"); } @@ -2674,6 +2805,9 @@ const char *SystemZTargetLowering::getTa OPCODE(SEARCH_STRING); OPCODE(IPM); OPCODE(SERIALIZE); + OPCODE(TBEGIN); + OPCODE(TBEGIN_NOFLOAT); + OPCODE(TEND); OPCODE(ATOMIC_SWAPW); OPCODE(ATOMIC_LOADW_ADD); OPCODE(ATOMIC_LOADW_SUB); @@ -3501,6 +3635,50 @@ SystemZTargetLowering::emitStringWrapper return DoneMBB; } +// Update TBEGIN instruction with final opcode and register clobbers. +MachineBasicBlock * +SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI, + MachineBasicBlock *MBB, + unsigned Opcode, + bool NoFloat) const { + MachineFunction &MF = *MBB->getParent(); + const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); + const SystemZInstrInfo *TII = Subtarget.getInstrInfo(); + + // Update opcode. + MI->setDesc(TII->get(Opcode)); + + // We cannot handle a TBEGIN that clobbers the stack or frame pointer. + // Make sure to add the corresponding GRSM bits if they are missing. + uint64_t Control = MI->getOperand(2).getImm(); + static const unsigned GPRControlBit[16] = { + 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000, + 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100 + }; + Control |= GPRControlBit[15]; + if (TFI->hasFP(MF)) + Control |= GPRControlBit[11]; + MI->getOperand(2).setImm(Control); + + // Add GPR clobbers. + for (int I = 0; I < 16; I++) { + if ((Control & GPRControlBit[I]) == 0) { + unsigned Reg = SystemZMC::GR64Regs[I]; + MI->addOperand(MachineOperand::CreateReg(Reg, true, true)); + } + } + + // Add FPR clobbers. + if (!NoFloat && (Control & 4) != 0) { + for (int I = 0; I < 16; I++) { + unsigned Reg = SystemZMC::FP64Regs[I]; + MI->addOperand(MachineOperand::CreateReg(Reg, true, true)); + } + } + + return MBB; +} + MachineBasicBlock *SystemZTargetLowering:: EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const { switch (MI->getOpcode()) { @@ -3742,6 +3920,12 @@ EmitInstrWithCustomInserter(MachineInstr return emitStringWrapper(MI, MBB, SystemZ::MVST); case SystemZ::SRSTLoop: return emitStringWrapper(MI, MBB, SystemZ::SRST); + case SystemZ::TBEGIN: + return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false); + case SystemZ::TBEGIN_nofloat: + return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true); + case SystemZ::TBEGINC: + return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true); default: llvm_unreachable("Unexpected instr type to insert"); } Index: llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll =================================================================== --- /dev/null +++ llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll @@ -0,0 +1,352 @@ +; Test transactional-execution intrinsics. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s + +declare i32 @llvm.s390.tbegin(i8 *, i32) +declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32) +declare void @llvm.s390.tbeginc(i8 *, i32) +declare i32 @llvm.s390.tend() +declare void @llvm.s390.tabort(i64) +declare void @llvm.s390.ntstg(i64, i64 *) +declare i32 @llvm.s390.etnd() +declare void @llvm.s390.ppa.txassist(i32) + +; TBEGIN. +define void @test_tbegin() { +; CHECK-LABEL: test_tbegin: +; CHECK-NOT: stmg +; CHECK: std %f8, +; CHECK: std %f9, +; CHECK: std %f10, +; CHECK: std %f11, +; CHECK: std %f12, +; CHECK: std %f13, +; CHECK: std %f14, +; CHECK: std %f15, +; CHECK: tbegin 0, 65292 +; CHECK: ld %f8, +; CHECK: ld %f9, +; CHECK: ld %f10, +; CHECK: ld %f11, +; CHECK: ld %f12, +; CHECK: ld %f13, +; CHECK: ld %f14, +; CHECK: ld %f15, +; CHECK: br %r14 + call i32 @llvm.s390.tbegin(i8 *null, i32 65292) + ret void +} + +; TBEGIN (nofloat). +define void @test_tbegin_nofloat1() { +; CHECK-LABEL: test_tbegin_nofloat1: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + ret void +} + +; TBEGIN (nofloat) with integer CC return value. +define i32 @test_tbegin_nofloat2() { +; CHECK-LABEL: test_tbegin_nofloat2: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + ret i32 %res +} + +; TBEGIN (nofloat) with implicit CC check. +define void @test_tbegin_nofloat3(i32 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat3: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: jnh {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +; TBEGIN (nofloat) with dual CC use. +define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat4: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: cijlh %r2, 2, {{\.L*}} +; CHECK: mvhi 0(%r3), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %res +} + +; TBEGIN (nofloat) with register. +define void @test_tbegin_nofloat5(i8 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat5: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0(%r2), 65292 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292) + ret void +} + +; TBEGIN (nofloat) with GRSM 0x0f00. +define void @test_tbegin_nofloat6() { +; CHECK-LABEL: test_tbegin_nofloat6: +; CHECK: stmg %r6, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 3840 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xf100. +define void @test_tbegin_nofloat7() { +; CHECK-LABEL: test_tbegin_nofloat7: +; CHECK: stmg %r8, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 61696 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically. +define void @test_tbegin_nofloat8() { +; CHECK-LABEL: test_tbegin_nofloat8: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65280 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed. +define void @test_tbegin_nofloat9() { +; CHECK-LABEL: test_tbegin_nofloat9: +; CHECK: stmg %r10, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 64256 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically. +define void @test_tbegin_nofloat10(i64 %n) { +; CHECK-LABEL: test_tbegin_nofloat10: +; CHECK: stmg %r11, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 65280 +; CHECK: br %r14 + %buf = alloca i8, i64 %n + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256) + ret void +} + +; TBEGINC. +define void @test_tbeginc() { +; CHECK-LABEL: test_tbeginc: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbeginc 0, 65288 +; CHECK: br %r14 + call void @llvm.s390.tbeginc(i8 *null, i32 65288) + ret void +} + +; TEND with integer CC return value. +define i32 @test_tend1() { +; CHECK-LABEL: test_tend1: +; CHECK: tend +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + ret i32 %res +} + +; TEND with implicit CC check. +define void @test_tend3(i32 *%ptr) { +; CHECK-LABEL: test_tend3: +; CHECK: tend +; CHECK: je {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +; TEND with dual CC use. +define i32 @test_tend2(i32 %pad, i32 *%ptr) { +; CHECK-LABEL: test_tend2: +; CHECK: tend +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: cijlh %r2, 2, {{\.L*}} +; CHECK: mvhi 0(%r3), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %res +} + +; TABORT with register only. +define void @test_tabort1(i64 %val) { +; CHECK-LABEL: test_tabort1: +; CHECK: tabort 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 %val) + ret void +} + +; TABORT with immediate only. +define void @test_tabort2(i64 %val) { +; CHECK-LABEL: test_tabort2: +; CHECK: tabort 1234 +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 1234) + ret void +} + +; TABORT with register + immediate. +define void @test_tabort3(i64 %val) { +; CHECK-LABEL: test_tabort3: +; CHECK: tabort 1234(%r2) +; CHECK: br %r14 + %sum = add i64 %val, 1234 + call void @llvm.s390.tabort(i64 %sum) + ret void +} + +; TABORT with out-of-range immediate. +define void @test_tabort4(i64 %val) { +; CHECK-LABEL: test_tabort4: +; CHECK: tabort 0({{%r[1-5]}}) +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 4096) + ret void +} + +; NTSTG with base pointer only. +define void @test_ntstg1(i64 *%ptr, i64 %val) { +; CHECK-LABEL: test_ntstg1: +; CHECK: ntstg %r3, 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with base and index. +; Check that VSTL doesn't allow an index. +define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) { +; CHECK-LABEL: test_ntstg2: +; CHECK: sllg [[REG:%r[1-5]]], %r3, 3 +; CHECK: ntstg %r4, 0([[REG]],%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 %index + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with the highest in-range displacement. +define void @test_ntstg3(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg3: +; CHECK: ntstg %r3, 524280(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 65535 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with an out-of-range positive displacement. +define void @test_ntstg4(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg4: +; CHECK: ntstg %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 65536 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with the lowest in-range displacement. +define void @test_ntstg5(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg5: +; CHECK: ntstg %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 -65536 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with an out-of-range negative displacement. +define void @test_ntstg6(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg6: +; CHECK: ntstg %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 -65537 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; ETND. +define i32 @test_etnd() { +; CHECK-LABEL: test_etnd: +; CHECK: etnd %r2 +; CHECK: br %r14 + %res = call i32 @llvm.s390.etnd() + ret i32 %res +} + +; PPA (Transaction-Abort Assist) +define void @test_ppa_txassist(i32 %val) { +; CHECK-LABEL: test_ppa_txassist: +; CHECK: ppa %r2, 0, 1 +; CHECK: br %r14 + call void @llvm.s390.ppa.txassist(i32 %val) + ret void +} + Index: llvm-head/test/MC/SystemZ/insn-bad-zEC12.s =================================================================== --- llvm-head.orig/test/MC/SystemZ/insn-bad-zEC12.s +++ llvm-head/test/MC/SystemZ/insn-bad-zEC12.s @@ -3,6 +3,22 @@ # RUN: FileCheck < %t %s #CHECK: error: invalid operand +#CHECK: ntstg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ntstg %r0, 524288 + + ntstg %r0, -524289 + ntstg %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: ppa %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: ppa %r0, %r0, 16 + + ppa %r0, %r0, -1 + ppa %r0, %r0, 16 + +#CHECK: error: invalid operand #CHECK: risbgn %r0,%r0,0,0,-1 #CHECK: error: invalid operand #CHECK: risbgn %r0,%r0,0,0,64 @@ -22,3 +38,47 @@ risbgn %r0,%r0,-1,0,0 risbgn %r0,%r0,256,0,0 +#CHECK: error: invalid operand +#CHECK: tabort -1 +#CHECK: error: invalid operand +#CHECK: tabort 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: tabort 0(%r1,%r2) + + tabort -1 + tabort 4096 + tabort 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: tbegin -1, 0 +#CHECK: error: invalid operand +#CHECK: tbegin 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: tbegin 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: tbegin 0, -1 +#CHECK: error: invalid operand +#CHECK: tbegin 0, 65536 + + tbegin -1, 0 + tbegin 4096, 0 + tbegin 0(%r1,%r2), 0 + tbegin 0, -1 + tbegin 0, 65536 + +#CHECK: error: invalid operand +#CHECK: tbeginc -1, 0 +#CHECK: error: invalid operand +#CHECK: tbeginc 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: tbeginc 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: tbeginc 0, -1 +#CHECK: error: invalid operand +#CHECK: tbeginc 0, 65536 + + tbeginc -1, 0 + tbeginc 4096, 0 + tbeginc 0(%r1,%r2), 0 + tbeginc 0, -1 + tbeginc 0, 65536 Index: llvm-head/test/MC/SystemZ/insn-good-zEC12.s =================================================================== --- llvm-head.orig/test/MC/SystemZ/insn-good-zEC12.s +++ llvm-head/test/MC/SystemZ/insn-good-zEC12.s @@ -1,6 +1,48 @@ # For zEC12 and above. # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s +#CHECK: etnd %r0 # encoding: [0xb2,0xec,0x00,0x00] +#CHECK: etnd %r15 # encoding: [0xb2,0xec,0x00,0xf0] +#CHECK: etnd %r7 # encoding: [0xb2,0xec,0x00,0x70] + + etnd %r0 + etnd %r15 + etnd %r7 + +#CHECK: ntstg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25] +#CHECK: ntstg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25] +#CHECK: ntstg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25] +#CHECK: ntstg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25] +#CHECK: ntstg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25] +#CHECK: ntstg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25] +#CHECK: ntstg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25] +#CHECK: ntstg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25] +#CHECK: ntstg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25] +#CHECK: ntstg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25] + + ntstg %r0, -524288 + ntstg %r0, -1 + ntstg %r0, 0 + ntstg %r0, 1 + ntstg %r0, 524287 + ntstg %r0, 0(%r1) + ntstg %r0, 0(%r15) + ntstg %r0, 524287(%r1,%r15) + ntstg %r0, 524287(%r15,%r1) + ntstg %r15, 0 + +#CHECK: ppa %r0, %r0, 0 # encoding: [0xb2,0xe8,0x00,0x00] +#CHECK: ppa %r0, %r0, 15 # encoding: [0xb2,0xe8,0xf0,0x00] +#CHECK: ppa %r0, %r15, 0 # encoding: [0xb2,0xe8,0x00,0x0f] +#CHECK: ppa %r4, %r6, 7 # encoding: [0xb2,0xe8,0x70,0x46] +#CHECK: ppa %r15, %r0, 0 # encoding: [0xb2,0xe8,0x00,0xf0] + + ppa %r0, %r0, 0 + ppa %r0, %r0, 15 + ppa %r0, %r15, 0 + ppa %r4, %r6, 7 + ppa %r15, %r0, 0 + #CHECK: risbgn %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x59] #CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59] #CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59] @@ -17,3 +59,68 @@ risbgn %r15,%r0,0,0,0 risbgn %r4,%r5,6,7,8 +#CHECK: tabort 0 # encoding: [0xb2,0xfc,0x00,0x00] +#CHECK: tabort 0(%r1) # encoding: [0xb2,0xfc,0x10,0x00] +#CHECK: tabort 0(%r15) # encoding: [0xb2,0xfc,0xf0,0x00] +#CHECK: tabort 4095 # encoding: [0xb2,0xfc,0x0f,0xff] +#CHECK: tabort 4095(%r1) # encoding: [0xb2,0xfc,0x1f,0xff] +#CHECK: tabort 4095(%r15) # encoding: [0xb2,0xfc,0xff,0xff] + + tabort 0 + tabort 0(%r1) + tabort 0(%r15) + tabort 4095 + tabort 4095(%r1) + tabort 4095(%r15) + +#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00] +#CHECK: tbegin 4095, 0 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00] +#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00] +#CHECK: tbegin 0, 1 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01] +#CHECK: tbegin 0, 32767 # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff] +#CHECK: tbegin 0, 32768 # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00] +#CHECK: tbegin 0, 65535 # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff] +#CHECK: tbegin 0(%r1), 42 # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a] +#CHECK: tbegin 0(%r15), 42 # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a] +#CHECK: tbegin 4095(%r1), 42 # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a] +#CHECK: tbegin 4095(%r15), 42 # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a] + + tbegin 0, 0 + tbegin 4095, 0 + tbegin 0, 0 + tbegin 0, 1 + tbegin 0, 32767 + tbegin 0, 32768 + tbegin 0, 65535 + tbegin 0(%r1), 42 + tbegin 0(%r15), 42 + tbegin 4095(%r1), 42 + tbegin 4095(%r15), 42 + +#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00] +#CHECK: tbeginc 4095, 0 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00] +#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00] +#CHECK: tbeginc 0, 1 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01] +#CHECK: tbeginc 0, 32767 # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff] +#CHECK: tbeginc 0, 32768 # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00] +#CHECK: tbeginc 0, 65535 # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff] +#CHECK: tbeginc 0(%r1), 42 # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a] +#CHECK: tbeginc 0(%r15), 42 # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a] +#CHECK: tbeginc 4095(%r1), 42 # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a] +#CHECK: tbeginc 4095(%r15), 42 # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a] + + tbeginc 0, 0 + tbeginc 4095, 0 + tbeginc 0, 0 + tbeginc 0, 1 + tbeginc 0, 32767 + tbeginc 0, 32768 + tbeginc 0, 65535 + tbeginc 0(%r1), 42 + tbeginc 0(%r15), 42 + tbeginc 4095(%r1), 42 + tbeginc 4095(%r15), 42 + +#CHECK: tend # encoding: [0xb2,0xf8,0x00,0x00] + + tend Index: llvm-head/test/MC/SystemZ/insn-bad-z196.s =================================================================== --- llvm-head.orig/test/MC/SystemZ/insn-bad-z196.s +++ llvm-head/test/MC/SystemZ/insn-bad-z196.s @@ -244,6 +244,11 @@ cxlgbr %f0, 16, %r0, 0 cxlgbr %f2, 0, %r0, 0 +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: etnd %r7 + + etnd %r7 + #CHECK: error: invalid operand #CHECK: fidbra %f0, 0, %f0, -1 #CHECK: error: invalid operand @@ -546,6 +551,16 @@ locr %r0,%r0,-1 locr %r0,%r0,16 +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: ntstg %r0, 524287(%r1,%r15) + + ntstg %r0, 524287(%r1,%r15) + +#CHECK: error: {{(instruction requires: processor-assist)?}} +#CHECK: ppa %r4, %r6, 7 + + ppa %r4, %r6, 7 + #CHECK: error: {{(instruction requires: miscellaneous-extensions)?}} #CHECK: risbgn %r1, %r2, 0, 0, 0 @@ -690,3 +705,24 @@ stocg %r0,-524289,1 stocg %r0,524288,1 stocg %r0,0(%r1,%r2),1 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tabort 4095(%r1) + + tabort 4095(%r1) + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tbegin 4095(%r1), 42 + + tbegin 4095(%r1), 42 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tbeginc 4095(%r1), 42 + + tbeginc 4095(%r1), 42 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tend + + tend + Index: llvm-head/test/MC/Disassembler/SystemZ/insns.txt =================================================================== --- llvm-head.orig/test/MC/Disassembler/SystemZ/insns.txt +++ llvm-head/test/MC/Disassembler/SystemZ/insns.txt @@ -2503,6 +2503,15 @@ # CHECK: ear %r15, %a15 0xb2 0x4f 0x00 0xff +# CHECK: etnd %r0 +0xb2 0xec 0x00 0x00 + +# CHECK: etnd %r15 +0xb2 0xec 0x00 0xf0 + +# CHECK: etnd %r7 +0xb2 0xec 0x00 0x70 + # CHECK: fidbr %f0, 0, %f0 0xb3 0x5f 0x00 0x00 @@ -6034,6 +6043,36 @@ # CHECK: ny %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x54 +# CHECK: ntstg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x25 + +# CHECK: ntstg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x25 + +# CHECK: ntstg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x25 + +# CHECK: ntstg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x25 + +# CHECK: ntstg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x25 + +# CHECK: ntstg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x25 + +# CHECK: ntstg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x25 + # CHECK: oc 0(1), 0 0xd6 0x00 0x00 0x00 0x00 0x00 @@ -6346,6 +6385,21 @@ # CHECK: popcnt %r7, %r8 0xb9 0xe1 0x00 0x78 +# CHECK: ppa %r0, %r0, 0 +0xb2 0xe8 0x00 0x00 + +# CHECK: ppa %r0, %r0, 15 +0xb2 0xe8 0xf0 0x00 + +# CHECK: ppa %r0, %r15, 0 +0xb2 0xe8 0x00 0x0f + +# CHECK: ppa %r4, %r6, 7 +0xb2 0xe8 0x70 0x46 + +# CHECK: ppa %r15, %r0, 0 +0xb2 0xe8 0x00 0xf0 + # CHECK: risbg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x55 @@ -8062,6 +8116,93 @@ # CHECK: sy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x5b +# CHECK: tabort 0 +0xb2 0xfc 0x00 0x00 + +# CHECK: tabort 0(%r1) +0xb2 0xfc 0x10 0x00 + +# CHECK: tabort 0(%r15) +0xb2 0xfc 0xf0 0x00 + +# CHECK: tabort 4095 +0xb2 0xfc 0x0f 0xff + +# CHECK: tabort 4095(%r1) +0xb2 0xfc 0x1f 0xff + +# CHECK: tabort 4095(%r15) +0xb2 0xfc 0xff 0xff + +# CHECK: tbegin 0, 0 +0xe5 0x60 0x00 0x00 0x00 0x00 + +# CHECK: tbegin 4095, 0 +0xe5 0x60 0x0f 0xff 0x00 0x00 + +# CHECK: tbegin 0, 0 +0xe5 0x60 0x00 0x00 0x00 0x00 + +# CHECK: tbegin 0, 1 +0xe5 0x60 0x00 0x00 0x00 0x01 + +# CHECK: tbegin 0, 32767 +0xe5 0x60 0x00 0x00 0x7f 0xff + +# CHECK: tbegin 0, 32768 +0xe5 0x60 0x00 0x00 0x80 0x00 + +# CHECK: tbegin 0, 65535 +0xe5 0x60 0x00 0x00 0xff 0xff + +# CHECK: tbegin 0(%r1), 42 +0xe5 0x60 0x10 0x00 0x00 0x2a + +# CHECK: tbegin 0(%r15), 42 +0xe5 0x60 0xf0 0x00 0x00 0x2a + +# CHECK: tbegin 4095(%r1), 42 +0xe5 0x60 0x1f 0xff 0x00 0x2a + +# CHECK: tbegin 4095(%r15), 42 +0xe5 0x60 0xff 0xff 0x00 0x2a + +# CHECK: tbeginc 0, 0 +0xe5 0x61 0x00 0x00 0x00 0x00 + +# CHECK: tbeginc 4095, 0 +0xe5 0x61 0x0f 0xff 0x00 0x00 + +# CHECK: tbeginc 0, 0 +0xe5 0x61 0x00 0x00 0x00 0x00 + +# CHECK: tbeginc 0, 1 +0xe5 0x61 0x00 0x00 0x00 0x01 + +# CHECK: tbeginc 0, 32767 +0xe5 0x61 0x00 0x00 0x7f 0xff + +# CHECK: tbeginc 0, 32768 +0xe5 0x61 0x00 0x00 0x80 0x00 + +# CHECK: tbeginc 0, 65535 +0xe5 0x61 0x00 0x00 0xff 0xff + +# CHECK: tbeginc 0(%r1), 42 +0xe5 0x61 0x10 0x00 0x00 0x2a + +# CHECK: tbeginc 0(%r15), 42 +0xe5 0x61 0xf0 0x00 0x00 0x2a + +# CHECK: tbeginc 4095(%r1), 42 +0xe5 0x61 0x1f 0xff 0x00 0x2a + +# CHECK: tbeginc 4095(%r15), 42 +0xe5 0x61 0xff 0xff 0x00 0x2a + +# CHECK: tend +0xb2 0xf8 0x00 0x00 + # CHECK: tm 0, 0 0x91 0x00 0x00 0x00 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233803 91177308-0d34-0410-b5e6-96231b3b80d8
1152 lines
36 KiB
C++
1152 lines
36 KiB
C++
//===--- Triple.cpp - Target triple helper class --------------------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/ADT/Triple.h"
|
|
#include "llvm/ADT/STLExtras.h"
|
|
#include "llvm/ADT/SmallString.h"
|
|
#include "llvm/ADT/StringSwitch.h"
|
|
#include "llvm/Support/ErrorHandling.h"
|
|
#include <cstring>
|
|
using namespace llvm;
|
|
|
|
const char *Triple::getArchTypeName(ArchType Kind) {
|
|
switch (Kind) {
|
|
case UnknownArch: return "unknown";
|
|
|
|
case aarch64: return "aarch64";
|
|
case aarch64_be: return "aarch64_be";
|
|
case arm: return "arm";
|
|
case armeb: return "armeb";
|
|
case bpf: return "bpf";
|
|
case hexagon: return "hexagon";
|
|
case mips: return "mips";
|
|
case mipsel: return "mipsel";
|
|
case mips64: return "mips64";
|
|
case mips64el: return "mips64el";
|
|
case msp430: return "msp430";
|
|
case ppc64: return "powerpc64";
|
|
case ppc64le: return "powerpc64le";
|
|
case ppc: return "powerpc";
|
|
case r600: return "r600";
|
|
case amdgcn: return "amdgcn";
|
|
case sparc: return "sparc";
|
|
case sparcv9: return "sparcv9";
|
|
case systemz: return "s390x";
|
|
case tce: return "tce";
|
|
case thumb: return "thumb";
|
|
case thumbeb: return "thumbeb";
|
|
case x86: return "i386";
|
|
case x86_64: return "x86_64";
|
|
case xcore: return "xcore";
|
|
case nvptx: return "nvptx";
|
|
case nvptx64: return "nvptx64";
|
|
case le32: return "le32";
|
|
case le64: return "le64";
|
|
case amdil: return "amdil";
|
|
case amdil64: return "amdil64";
|
|
case hsail: return "hsail";
|
|
case hsail64: return "hsail64";
|
|
case spir: return "spir";
|
|
case spir64: return "spir64";
|
|
case kalimba: return "kalimba";
|
|
}
|
|
|
|
llvm_unreachable("Invalid ArchType!");
|
|
}
|
|
|
|
const char *Triple::getArchTypePrefix(ArchType Kind) {
|
|
switch (Kind) {
|
|
default:
|
|
return nullptr;
|
|
|
|
case aarch64:
|
|
case aarch64_be: return "aarch64";
|
|
|
|
case arm:
|
|
case armeb:
|
|
case thumb:
|
|
case thumbeb: return "arm";
|
|
|
|
case ppc64:
|
|
case ppc64le:
|
|
case ppc: return "ppc";
|
|
|
|
case mips:
|
|
case mipsel:
|
|
case mips64:
|
|
case mips64el: return "mips";
|
|
|
|
case hexagon: return "hexagon";
|
|
|
|
case amdgcn:
|
|
case r600: return "amdgpu";
|
|
|
|
case bpf: return "bpf";
|
|
|
|
case sparcv9:
|
|
case sparc: return "sparc";
|
|
|
|
case systemz: return "s390";
|
|
|
|
case x86:
|
|
case x86_64: return "x86";
|
|
|
|
case xcore: return "xcore";
|
|
|
|
case nvptx: return "nvptx";
|
|
case nvptx64: return "nvptx";
|
|
|
|
case le32: return "le32";
|
|
case le64: return "le64";
|
|
|
|
case amdil:
|
|
case amdil64: return "amdil";
|
|
|
|
case hsail:
|
|
case hsail64: return "hsail";
|
|
|
|
case spir:
|
|
case spir64: return "spir";
|
|
case kalimba: return "kalimba";
|
|
}
|
|
}
|
|
|
|
const char *Triple::getVendorTypeName(VendorType Kind) {
|
|
switch (Kind) {
|
|
case UnknownVendor: return "unknown";
|
|
|
|
case Apple: return "apple";
|
|
case PC: return "pc";
|
|
case SCEI: return "scei";
|
|
case BGP: return "bgp";
|
|
case BGQ: return "bgq";
|
|
case Freescale: return "fsl";
|
|
case IBM: return "ibm";
|
|
case ImaginationTechnologies: return "img";
|
|
case MipsTechnologies: return "mti";
|
|
case NVIDIA: return "nvidia";
|
|
case CSR: return "csr";
|
|
}
|
|
|
|
llvm_unreachable("Invalid VendorType!");
|
|
}
|
|
|
|
const char *Triple::getOSTypeName(OSType Kind) {
|
|
switch (Kind) {
|
|
case UnknownOS: return "unknown";
|
|
|
|
case CloudABI: return "cloudabi";
|
|
case Darwin: return "darwin";
|
|
case DragonFly: return "dragonfly";
|
|
case FreeBSD: return "freebsd";
|
|
case IOS: return "ios";
|
|
case KFreeBSD: return "kfreebsd";
|
|
case Linux: return "linux";
|
|
case Lv2: return "lv2";
|
|
case MacOSX: return "macosx";
|
|
case NetBSD: return "netbsd";
|
|
case OpenBSD: return "openbsd";
|
|
case Solaris: return "solaris";
|
|
case Win32: return "windows";
|
|
case Haiku: return "haiku";
|
|
case Minix: return "minix";
|
|
case RTEMS: return "rtems";
|
|
case NaCl: return "nacl";
|
|
case CNK: return "cnk";
|
|
case Bitrig: return "bitrig";
|
|
case AIX: return "aix";
|
|
case CUDA: return "cuda";
|
|
case NVCL: return "nvcl";
|
|
case AMDHSA: return "amdhsa";
|
|
case PS4: return "ps4";
|
|
}
|
|
|
|
llvm_unreachable("Invalid OSType");
|
|
}
|
|
|
|
const char *Triple::getEnvironmentTypeName(EnvironmentType Kind) {
|
|
switch (Kind) {
|
|
case UnknownEnvironment: return "unknown";
|
|
case GNU: return "gnu";
|
|
case GNUEABIHF: return "gnueabihf";
|
|
case GNUEABI: return "gnueabi";
|
|
case GNUX32: return "gnux32";
|
|
case CODE16: return "code16";
|
|
case EABI: return "eabi";
|
|
case EABIHF: return "eabihf";
|
|
case Android: return "android";
|
|
case MSVC: return "msvc";
|
|
case Itanium: return "itanium";
|
|
case Cygnus: return "cygnus";
|
|
}
|
|
|
|
llvm_unreachable("Invalid EnvironmentType!");
|
|
}
|
|
|
|
Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
|
|
return StringSwitch<Triple::ArchType>(Name)
|
|
.Case("aarch64", aarch64)
|
|
.Case("aarch64_be", aarch64_be)
|
|
.Case("arm64", aarch64) // "arm64" is an alias for "aarch64"
|
|
.Case("arm", arm)
|
|
.Case("armeb", armeb)
|
|
.Case("bpf", bpf)
|
|
.Case("mips", mips)
|
|
.Case("mipsel", mipsel)
|
|
.Case("mips64", mips64)
|
|
.Case("mips64el", mips64el)
|
|
.Case("msp430", msp430)
|
|
.Case("ppc64", ppc64)
|
|
.Case("ppc32", ppc)
|
|
.Case("ppc", ppc)
|
|
.Case("ppc64le", ppc64le)
|
|
.Case("r600", r600)
|
|
.Case("amdgcn", amdgcn)
|
|
.Case("hexagon", hexagon)
|
|
.Case("sparc", sparc)
|
|
.Case("sparcv9", sparcv9)
|
|
.Case("systemz", systemz)
|
|
.Case("tce", tce)
|
|
.Case("thumb", thumb)
|
|
.Case("thumbeb", thumbeb)
|
|
.Case("x86", x86)
|
|
.Case("x86-64", x86_64)
|
|
.Case("xcore", xcore)
|
|
.Case("nvptx", nvptx)
|
|
.Case("nvptx64", nvptx64)
|
|
.Case("le32", le32)
|
|
.Case("le64", le64)
|
|
.Case("amdil", amdil)
|
|
.Case("amdil64", amdil64)
|
|
.Case("hsail", hsail)
|
|
.Case("hsail64", hsail64)
|
|
.Case("spir", spir)
|
|
.Case("spir64", spir64)
|
|
.Case("kalimba", kalimba)
|
|
.Default(UnknownArch);
|
|
}
|
|
|
|
static Triple::ArchType parseARMArch(StringRef ArchName) {
|
|
size_t offset = StringRef::npos;
|
|
Triple::ArchType arch = Triple::UnknownArch;
|
|
bool isThumb = ArchName.startswith("thumb");
|
|
|
|
if (ArchName.equals("arm"))
|
|
return Triple::arm;
|
|
if (ArchName.equals("armeb"))
|
|
return Triple::armeb;
|
|
if (ArchName.equals("thumb"))
|
|
return Triple::thumb;
|
|
if (ArchName.equals("thumbeb"))
|
|
return Triple::thumbeb;
|
|
if (ArchName.equals("arm64") || ArchName.equals("aarch64"))
|
|
return Triple::aarch64;
|
|
if (ArchName.equals("aarch64_be"))
|
|
return Triple::aarch64_be;
|
|
|
|
if (ArchName.startswith("armv")) {
|
|
offset = 3;
|
|
if (ArchName.endswith("eb")) {
|
|
arch = Triple::armeb;
|
|
ArchName = ArchName.substr(0, ArchName.size() - 2);
|
|
} else
|
|
arch = Triple::arm;
|
|
} else if (ArchName.startswith("armebv")) {
|
|
offset = 5;
|
|
arch = Triple::armeb;
|
|
} else if (ArchName.startswith("thumbv")) {
|
|
offset = 5;
|
|
if (ArchName.endswith("eb")) {
|
|
arch = Triple::thumbeb;
|
|
ArchName = ArchName.substr(0, ArchName.size() - 2);
|
|
} else
|
|
arch = Triple::thumb;
|
|
} else if (ArchName.startswith("thumbebv")) {
|
|
offset = 7;
|
|
arch = Triple::thumbeb;
|
|
}
|
|
return StringSwitch<Triple::ArchType>(ArchName.substr(offset))
|
|
.Cases("v2", "v2a", isThumb ? Triple::UnknownArch : arch)
|
|
.Cases("v3", "v3m", isThumb ? Triple::UnknownArch : arch)
|
|
.Cases("v4", "v4t", arch)
|
|
.Cases("v5", "v5e", "v5t", "v5te", "v5tej", arch)
|
|
.Cases("v6", "v6j", "v6k", "v6m", "v6sm", arch)
|
|
.Cases("v6t2", "v6z", "v6zk", arch)
|
|
.Cases("v7", "v7a", "v7em", "v7l", arch)
|
|
.Cases("v7m", "v7r", "v7s", arch)
|
|
.Cases("v8", "v8a", arch)
|
|
.Cases("v8.1", "v8.1a", arch)
|
|
.Default(Triple::UnknownArch);
|
|
}
|
|
|
|
static Triple::ArchType parseArch(StringRef ArchName) {
|
|
Triple::ArchType ARMArch(parseARMArch(ArchName));
|
|
|
|
return StringSwitch<Triple::ArchType>(ArchName)
|
|
.Cases("i386", "i486", "i586", "i686", Triple::x86)
|
|
// FIXME: Do we need to support these?
|
|
.Cases("i786", "i886", "i986", Triple::x86)
|
|
.Cases("amd64", "x86_64", "x86_64h", Triple::x86_64)
|
|
.Case("powerpc", Triple::ppc)
|
|
.Cases("powerpc64", "ppu", Triple::ppc64)
|
|
.Case("powerpc64le", Triple::ppc64le)
|
|
.Case("xscale", Triple::arm)
|
|
.Case("xscaleeb", Triple::armeb)
|
|
.StartsWith("arm", ARMArch)
|
|
.StartsWith("thumb", ARMArch)
|
|
.StartsWith("aarch64", ARMArch)
|
|
.Case("msp430", Triple::msp430)
|
|
.Cases("mips", "mipseb", "mipsallegrex", Triple::mips)
|
|
.Cases("mipsel", "mipsallegrexel", Triple::mipsel)
|
|
.Cases("mips64", "mips64eb", Triple::mips64)
|
|
.Case("mips64el", Triple::mips64el)
|
|
.Case("r600", Triple::r600)
|
|
.Case("amdgcn", Triple::amdgcn)
|
|
.Case("bpf", Triple::bpf)
|
|
.Case("hexagon", Triple::hexagon)
|
|
.Case("s390x", Triple::systemz)
|
|
.Case("sparc", Triple::sparc)
|
|
.Cases("sparcv9", "sparc64", Triple::sparcv9)
|
|
.Case("tce", Triple::tce)
|
|
.Case("xcore", Triple::xcore)
|
|
.Case("nvptx", Triple::nvptx)
|
|
.Case("nvptx64", Triple::nvptx64)
|
|
.Case("le32", Triple::le32)
|
|
.Case("le64", Triple::le64)
|
|
.Case("amdil", Triple::amdil)
|
|
.Case("amdil64", Triple::amdil64)
|
|
.Case("hsail", Triple::hsail)
|
|
.Case("hsail64", Triple::hsail64)
|
|
.Case("spir", Triple::spir)
|
|
.Case("spir64", Triple::spir64)
|
|
.StartsWith("kalimba", Triple::kalimba)
|
|
.Default(Triple::UnknownArch);
|
|
}
|
|
|
|
static Triple::VendorType parseVendor(StringRef VendorName) {
|
|
return StringSwitch<Triple::VendorType>(VendorName)
|
|
.Case("apple", Triple::Apple)
|
|
.Case("pc", Triple::PC)
|
|
.Case("scei", Triple::SCEI)
|
|
.Case("bgp", Triple::BGP)
|
|
.Case("bgq", Triple::BGQ)
|
|
.Case("fsl", Triple::Freescale)
|
|
.Case("ibm", Triple::IBM)
|
|
.Case("img", Triple::ImaginationTechnologies)
|
|
.Case("mti", Triple::MipsTechnologies)
|
|
.Case("nvidia", Triple::NVIDIA)
|
|
.Case("csr", Triple::CSR)
|
|
.Default(Triple::UnknownVendor);
|
|
}
|
|
|
|
static Triple::OSType parseOS(StringRef OSName) {
|
|
return StringSwitch<Triple::OSType>(OSName)
|
|
.StartsWith("cloudabi", Triple::CloudABI)
|
|
.StartsWith("darwin", Triple::Darwin)
|
|
.StartsWith("dragonfly", Triple::DragonFly)
|
|
.StartsWith("freebsd", Triple::FreeBSD)
|
|
.StartsWith("ios", Triple::IOS)
|
|
.StartsWith("kfreebsd", Triple::KFreeBSD)
|
|
.StartsWith("linux", Triple::Linux)
|
|
.StartsWith("lv2", Triple::Lv2)
|
|
.StartsWith("macosx", Triple::MacOSX)
|
|
.StartsWith("netbsd", Triple::NetBSD)
|
|
.StartsWith("openbsd", Triple::OpenBSD)
|
|
.StartsWith("solaris", Triple::Solaris)
|
|
.StartsWith("win32", Triple::Win32)
|
|
.StartsWith("windows", Triple::Win32)
|
|
.StartsWith("haiku", Triple::Haiku)
|
|
.StartsWith("minix", Triple::Minix)
|
|
.StartsWith("rtems", Triple::RTEMS)
|
|
.StartsWith("nacl", Triple::NaCl)
|
|
.StartsWith("cnk", Triple::CNK)
|
|
.StartsWith("bitrig", Triple::Bitrig)
|
|
.StartsWith("aix", Triple::AIX)
|
|
.StartsWith("cuda", Triple::CUDA)
|
|
.StartsWith("nvcl", Triple::NVCL)
|
|
.StartsWith("amdhsa", Triple::AMDHSA)
|
|
.StartsWith("ps4", Triple::PS4)
|
|
.Default(Triple::UnknownOS);
|
|
}
|
|
|
|
static Triple::EnvironmentType parseEnvironment(StringRef EnvironmentName) {
|
|
return StringSwitch<Triple::EnvironmentType>(EnvironmentName)
|
|
.StartsWith("eabihf", Triple::EABIHF)
|
|
.StartsWith("eabi", Triple::EABI)
|
|
.StartsWith("gnueabihf", Triple::GNUEABIHF)
|
|
.StartsWith("gnueabi", Triple::GNUEABI)
|
|
.StartsWith("gnux32", Triple::GNUX32)
|
|
.StartsWith("code16", Triple::CODE16)
|
|
.StartsWith("gnu", Triple::GNU)
|
|
.StartsWith("android", Triple::Android)
|
|
.StartsWith("msvc", Triple::MSVC)
|
|
.StartsWith("itanium", Triple::Itanium)
|
|
.StartsWith("cygnus", Triple::Cygnus)
|
|
.Default(Triple::UnknownEnvironment);
|
|
}
|
|
|
|
static Triple::ObjectFormatType parseFormat(StringRef EnvironmentName) {
|
|
return StringSwitch<Triple::ObjectFormatType>(EnvironmentName)
|
|
.EndsWith("coff", Triple::COFF)
|
|
.EndsWith("elf", Triple::ELF)
|
|
.EndsWith("macho", Triple::MachO)
|
|
.Default(Triple::UnknownObjectFormat);
|
|
}
|
|
|
|
static Triple::SubArchType parseSubArch(StringRef SubArchName) {
|
|
if (SubArchName.endswith("eb"))
|
|
SubArchName = SubArchName.substr(0, SubArchName.size() - 2);
|
|
|
|
return StringSwitch<Triple::SubArchType>(SubArchName)
|
|
.EndsWith("v8.1a", Triple::ARMSubArch_v8_1a)
|
|
.EndsWith("v8", Triple::ARMSubArch_v8)
|
|
.EndsWith("v8a", Triple::ARMSubArch_v8)
|
|
.EndsWith("v7", Triple::ARMSubArch_v7)
|
|
.EndsWith("v7a", Triple::ARMSubArch_v7)
|
|
.EndsWith("v7em", Triple::ARMSubArch_v7em)
|
|
.EndsWith("v7l", Triple::ARMSubArch_v7)
|
|
.EndsWith("v7m", Triple::ARMSubArch_v7m)
|
|
.EndsWith("v7r", Triple::ARMSubArch_v7)
|
|
.EndsWith("v7s", Triple::ARMSubArch_v7s)
|
|
.EndsWith("v6", Triple::ARMSubArch_v6)
|
|
.EndsWith("v6m", Triple::ARMSubArch_v6m)
|
|
.EndsWith("v6sm", Triple::ARMSubArch_v6m)
|
|
.EndsWith("v6k", Triple::ARMSubArch_v6k)
|
|
.EndsWith("v6t2", Triple::ARMSubArch_v6t2)
|
|
.EndsWith("v5", Triple::ARMSubArch_v5)
|
|
.EndsWith("v5e", Triple::ARMSubArch_v5)
|
|
.EndsWith("v5t", Triple::ARMSubArch_v5)
|
|
.EndsWith("v5te", Triple::ARMSubArch_v5te)
|
|
.EndsWith("v4t", Triple::ARMSubArch_v4t)
|
|
.EndsWith("kalimba3", Triple::KalimbaSubArch_v3)
|
|
.EndsWith("kalimba4", Triple::KalimbaSubArch_v4)
|
|
.EndsWith("kalimba5", Triple::KalimbaSubArch_v5)
|
|
.Default(Triple::NoSubArch);
|
|
}
|
|
|
|
static const char *getObjectFormatTypeName(Triple::ObjectFormatType Kind) {
|
|
switch (Kind) {
|
|
case Triple::UnknownObjectFormat: return "";
|
|
case Triple::COFF: return "coff";
|
|
case Triple::ELF: return "elf";
|
|
case Triple::MachO: return "macho";
|
|
}
|
|
llvm_unreachable("unknown object format type");
|
|
}
|
|
|
|
static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
|
|
switch (T.getArch()) {
|
|
default:
|
|
break;
|
|
case Triple::hexagon:
|
|
case Triple::mips:
|
|
case Triple::mipsel:
|
|
case Triple::mips64:
|
|
case Triple::mips64el:
|
|
case Triple::r600:
|
|
case Triple::amdgcn:
|
|
case Triple::sparc:
|
|
case Triple::sparcv9:
|
|
case Triple::systemz:
|
|
case Triple::xcore:
|
|
case Triple::ppc64le:
|
|
return Triple::ELF;
|
|
|
|
case Triple::ppc:
|
|
case Triple::ppc64:
|
|
if (T.isOSDarwin())
|
|
return Triple::MachO;
|
|
return Triple::ELF;
|
|
}
|
|
|
|
if (T.isOSDarwin())
|
|
return Triple::MachO;
|
|
else if (T.isOSWindows())
|
|
return Triple::COFF;
|
|
return Triple::ELF;
|
|
}
|
|
|
|
/// \brief Construct a triple from the string representation provided.
|
|
///
|
|
/// This stores the string representation and parses the various pieces into
|
|
/// enum members.
|
|
Triple::Triple(const Twine &Str)
|
|
: Data(Str.str()),
|
|
Arch(parseArch(getArchName())),
|
|
SubArch(parseSubArch(getArchName())),
|
|
Vendor(parseVendor(getVendorName())),
|
|
OS(parseOS(getOSName())),
|
|
Environment(parseEnvironment(getEnvironmentName())),
|
|
ObjectFormat(parseFormat(getEnvironmentName())) {
|
|
if (ObjectFormat == Triple::UnknownObjectFormat)
|
|
ObjectFormat = getDefaultFormat(*this);
|
|
}
|
|
|
|
/// \brief Construct a triple from string representations of the architecture,
|
|
/// vendor, and OS.
|
|
///
|
|
/// This joins each argument into a canonical string representation and parses
|
|
/// them into enum members. It leaves the environment unknown and omits it from
|
|
/// the string representation.
|
|
Triple::Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr)
|
|
: Data((ArchStr + Twine('-') + VendorStr + Twine('-') + OSStr).str()),
|
|
Arch(parseArch(ArchStr.str())),
|
|
SubArch(parseSubArch(ArchStr.str())),
|
|
Vendor(parseVendor(VendorStr.str())),
|
|
OS(parseOS(OSStr.str())),
|
|
Environment(), ObjectFormat(Triple::UnknownObjectFormat) {
|
|
ObjectFormat = getDefaultFormat(*this);
|
|
}
|
|
|
|
/// \brief Construct a triple from string representations of the architecture,
|
|
/// vendor, OS, and environment.
|
|
///
|
|
/// This joins each argument into a canonical string representation and parses
|
|
/// them into enum members.
|
|
Triple::Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr,
|
|
const Twine &EnvironmentStr)
|
|
: Data((ArchStr + Twine('-') + VendorStr + Twine('-') + OSStr + Twine('-') +
|
|
EnvironmentStr).str()),
|
|
Arch(parseArch(ArchStr.str())),
|
|
SubArch(parseSubArch(ArchStr.str())),
|
|
Vendor(parseVendor(VendorStr.str())),
|
|
OS(parseOS(OSStr.str())),
|
|
Environment(parseEnvironment(EnvironmentStr.str())),
|
|
ObjectFormat(parseFormat(EnvironmentStr.str())) {
|
|
if (ObjectFormat == Triple::UnknownObjectFormat)
|
|
ObjectFormat = getDefaultFormat(*this);
|
|
}
|
|
|
|
std::string Triple::normalize(StringRef Str) {
|
|
bool IsMinGW32 = false;
|
|
bool IsCygwin = false;
|
|
|
|
// Parse into components.
|
|
SmallVector<StringRef, 4> Components;
|
|
Str.split(Components, "-");
|
|
|
|
// If the first component corresponds to a known architecture, preferentially
|
|
// use it for the architecture. If the second component corresponds to a
|
|
// known vendor, preferentially use it for the vendor, etc. This avoids silly
|
|
// component movement when a component parses as (eg) both a valid arch and a
|
|
// valid os.
|
|
ArchType Arch = UnknownArch;
|
|
if (Components.size() > 0)
|
|
Arch = parseArch(Components[0]);
|
|
VendorType Vendor = UnknownVendor;
|
|
if (Components.size() > 1)
|
|
Vendor = parseVendor(Components[1]);
|
|
OSType OS = UnknownOS;
|
|
if (Components.size() > 2) {
|
|
OS = parseOS(Components[2]);
|
|
IsCygwin = Components[2].startswith("cygwin");
|
|
IsMinGW32 = Components[2].startswith("mingw");
|
|
}
|
|
EnvironmentType Environment = UnknownEnvironment;
|
|
if (Components.size() > 3)
|
|
Environment = parseEnvironment(Components[3]);
|
|
ObjectFormatType ObjectFormat = UnknownObjectFormat;
|
|
if (Components.size() > 4)
|
|
ObjectFormat = parseFormat(Components[4]);
|
|
|
|
// Note which components are already in their final position. These will not
|
|
// be moved.
|
|
bool Found[4];
|
|
Found[0] = Arch != UnknownArch;
|
|
Found[1] = Vendor != UnknownVendor;
|
|
Found[2] = OS != UnknownOS;
|
|
Found[3] = Environment != UnknownEnvironment;
|
|
|
|
// If they are not there already, permute the components into their canonical
|
|
// positions by seeing if they parse as a valid architecture, and if so moving
|
|
// the component to the architecture position etc.
|
|
for (unsigned Pos = 0; Pos != array_lengthof(Found); ++Pos) {
|
|
if (Found[Pos])
|
|
continue; // Already in the canonical position.
|
|
|
|
for (unsigned Idx = 0; Idx != Components.size(); ++Idx) {
|
|
// Do not reparse any components that already matched.
|
|
if (Idx < array_lengthof(Found) && Found[Idx])
|
|
continue;
|
|
|
|
// Does this component parse as valid for the target position?
|
|
bool Valid = false;
|
|
StringRef Comp = Components[Idx];
|
|
switch (Pos) {
|
|
default: llvm_unreachable("unexpected component type!");
|
|
case 0:
|
|
Arch = parseArch(Comp);
|
|
Valid = Arch != UnknownArch;
|
|
break;
|
|
case 1:
|
|
Vendor = parseVendor(Comp);
|
|
Valid = Vendor != UnknownVendor;
|
|
break;
|
|
case 2:
|
|
OS = parseOS(Comp);
|
|
IsCygwin = Comp.startswith("cygwin");
|
|
IsMinGW32 = Comp.startswith("mingw");
|
|
Valid = OS != UnknownOS || IsCygwin || IsMinGW32;
|
|
break;
|
|
case 3:
|
|
Environment = parseEnvironment(Comp);
|
|
Valid = Environment != UnknownEnvironment;
|
|
if (!Valid) {
|
|
ObjectFormat = parseFormat(Comp);
|
|
Valid = ObjectFormat != UnknownObjectFormat;
|
|
}
|
|
break;
|
|
}
|
|
if (!Valid)
|
|
continue; // Nope, try the next component.
|
|
|
|
// Move the component to the target position, pushing any non-fixed
|
|
// components that are in the way to the right. This tends to give
|
|
// good results in the common cases of a forgotten vendor component
|
|
// or a wrongly positioned environment.
|
|
if (Pos < Idx) {
|
|
// Insert left, pushing the existing components to the right. For
|
|
// example, a-b-i386 -> i386-a-b when moving i386 to the front.
|
|
StringRef CurrentComponent(""); // The empty component.
|
|
// Replace the component we are moving with an empty component.
|
|
std::swap(CurrentComponent, Components[Idx]);
|
|
// Insert the component being moved at Pos, displacing any existing
|
|
// components to the right.
|
|
for (unsigned i = Pos; !CurrentComponent.empty(); ++i) {
|
|
// Skip over any fixed components.
|
|
while (i < array_lengthof(Found) && Found[i])
|
|
++i;
|
|
// Place the component at the new position, getting the component
|
|
// that was at this position - it will be moved right.
|
|
std::swap(CurrentComponent, Components[i]);
|
|
}
|
|
} else if (Pos > Idx) {
|
|
// Push right by inserting empty components until the component at Idx
|
|
// reaches the target position Pos. For example, pc-a -> -pc-a when
|
|
// moving pc to the second position.
|
|
do {
|
|
// Insert one empty component at Idx.
|
|
StringRef CurrentComponent(""); // The empty component.
|
|
for (unsigned i = Idx; i < Components.size();) {
|
|
// Place the component at the new position, getting the component
|
|
// that was at this position - it will be moved right.
|
|
std::swap(CurrentComponent, Components[i]);
|
|
// If it was placed on top of an empty component then we are done.
|
|
if (CurrentComponent.empty())
|
|
break;
|
|
// Advance to the next component, skipping any fixed components.
|
|
while (++i < array_lengthof(Found) && Found[i])
|
|
;
|
|
}
|
|
// The last component was pushed off the end - append it.
|
|
if (!CurrentComponent.empty())
|
|
Components.push_back(CurrentComponent);
|
|
|
|
// Advance Idx to the component's new position.
|
|
while (++Idx < array_lengthof(Found) && Found[Idx])
|
|
;
|
|
} while (Idx < Pos); // Add more until the final position is reached.
|
|
}
|
|
assert(Pos < Components.size() && Components[Pos] == Comp &&
|
|
"Component moved wrong!");
|
|
Found[Pos] = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Special case logic goes here. At this point Arch, Vendor and OS have the
|
|
// correct values for the computed components.
|
|
|
|
if (OS == Triple::Win32) {
|
|
Components.resize(4);
|
|
Components[2] = "windows";
|
|
if (Environment == UnknownEnvironment) {
|
|
if (ObjectFormat == UnknownObjectFormat || ObjectFormat == Triple::COFF)
|
|
Components[3] = "msvc";
|
|
else
|
|
Components[3] = getObjectFormatTypeName(ObjectFormat);
|
|
}
|
|
} else if (IsMinGW32) {
|
|
Components.resize(4);
|
|
Components[2] = "windows";
|
|
Components[3] = "gnu";
|
|
} else if (IsCygwin) {
|
|
Components.resize(4);
|
|
Components[2] = "windows";
|
|
Components[3] = "cygnus";
|
|
}
|
|
if (IsMinGW32 || IsCygwin ||
|
|
(OS == Triple::Win32 && Environment != UnknownEnvironment)) {
|
|
if (ObjectFormat != UnknownObjectFormat && ObjectFormat != Triple::COFF) {
|
|
Components.resize(5);
|
|
Components[4] = getObjectFormatTypeName(ObjectFormat);
|
|
}
|
|
}
|
|
|
|
// Stick the corrected components back together to form the normalized string.
|
|
std::string Normalized;
|
|
for (unsigned i = 0, e = Components.size(); i != e; ++i) {
|
|
if (i) Normalized += '-';
|
|
Normalized += Components[i];
|
|
}
|
|
return Normalized;
|
|
}
|
|
|
|
StringRef Triple::getArchName() const {
|
|
return StringRef(Data).split('-').first; // Isolate first component
|
|
}
|
|
|
|
StringRef Triple::getVendorName() const {
|
|
StringRef Tmp = StringRef(Data).split('-').second; // Strip first component
|
|
return Tmp.split('-').first; // Isolate second component
|
|
}
|
|
|
|
StringRef Triple::getOSName() const {
|
|
StringRef Tmp = StringRef(Data).split('-').second; // Strip first component
|
|
Tmp = Tmp.split('-').second; // Strip second component
|
|
return Tmp.split('-').first; // Isolate third component
|
|
}
|
|
|
|
StringRef Triple::getEnvironmentName() const {
|
|
StringRef Tmp = StringRef(Data).split('-').second; // Strip first component
|
|
Tmp = Tmp.split('-').second; // Strip second component
|
|
return Tmp.split('-').second; // Strip third component
|
|
}
|
|
|
|
StringRef Triple::getOSAndEnvironmentName() const {
|
|
StringRef Tmp = StringRef(Data).split('-').second; // Strip first component
|
|
return Tmp.split('-').second; // Strip second component
|
|
}
|
|
|
|
static unsigned EatNumber(StringRef &Str) {
|
|
assert(!Str.empty() && Str[0] >= '0' && Str[0] <= '9' && "Not a number");
|
|
unsigned Result = 0;
|
|
|
|
do {
|
|
// Consume the leading digit.
|
|
Result = Result*10 + (Str[0] - '0');
|
|
|
|
// Eat the digit.
|
|
Str = Str.substr(1);
|
|
} while (!Str.empty() && Str[0] >= '0' && Str[0] <= '9');
|
|
|
|
return Result;
|
|
}
|
|
|
|
void Triple::getOSVersion(unsigned &Major, unsigned &Minor,
|
|
unsigned &Micro) const {
|
|
StringRef OSName = getOSName();
|
|
|
|
// For Android, we care about the Android version rather than the Linux
|
|
// version.
|
|
if (getEnvironment() == Android) {
|
|
OSName = getEnvironmentName().substr(strlen("android"));
|
|
if (OSName.startswith("eabi"))
|
|
OSName = OSName.substr(strlen("eabi"));
|
|
}
|
|
|
|
// Assume that the OS portion of the triple starts with the canonical name.
|
|
StringRef OSTypeName = getOSTypeName(getOS());
|
|
if (OSName.startswith(OSTypeName))
|
|
OSName = OSName.substr(OSTypeName.size());
|
|
|
|
// Any unset version defaults to 0.
|
|
Major = Minor = Micro = 0;
|
|
|
|
// Parse up to three components.
|
|
unsigned *Components[3] = { &Major, &Minor, &Micro };
|
|
for (unsigned i = 0; i != 3; ++i) {
|
|
if (OSName.empty() || OSName[0] < '0' || OSName[0] > '9')
|
|
break;
|
|
|
|
// Consume the leading number.
|
|
*Components[i] = EatNumber(OSName);
|
|
|
|
// Consume the separator, if present.
|
|
if (OSName.startswith("."))
|
|
OSName = OSName.substr(1);
|
|
}
|
|
}
|
|
|
|
bool Triple::getMacOSXVersion(unsigned &Major, unsigned &Minor,
|
|
unsigned &Micro) const {
|
|
getOSVersion(Major, Minor, Micro);
|
|
|
|
switch (getOS()) {
|
|
default: llvm_unreachable("unexpected OS for Darwin triple");
|
|
case Darwin:
|
|
// Default to darwin8, i.e., MacOSX 10.4.
|
|
if (Major == 0)
|
|
Major = 8;
|
|
// Darwin version numbers are skewed from OS X versions.
|
|
if (Major < 4)
|
|
return false;
|
|
Micro = 0;
|
|
Minor = Major - 4;
|
|
Major = 10;
|
|
break;
|
|
case MacOSX:
|
|
// Default to 10.4.
|
|
if (Major == 0) {
|
|
Major = 10;
|
|
Minor = 4;
|
|
}
|
|
if (Major != 10)
|
|
return false;
|
|
break;
|
|
case IOS:
|
|
// Ignore the version from the triple. This is only handled because the
|
|
// the clang driver combines OS X and IOS support into a common Darwin
|
|
// toolchain that wants to know the OS X version number even when targeting
|
|
// IOS.
|
|
Major = 10;
|
|
Minor = 4;
|
|
Micro = 0;
|
|
break;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
void Triple::getiOSVersion(unsigned &Major, unsigned &Minor,
|
|
unsigned &Micro) const {
|
|
switch (getOS()) {
|
|
default: llvm_unreachable("unexpected OS for Darwin triple");
|
|
case Darwin:
|
|
case MacOSX:
|
|
// Ignore the version from the triple. This is only handled because the
|
|
// the clang driver combines OS X and IOS support into a common Darwin
|
|
// toolchain that wants to know the iOS version number even when targeting
|
|
// OS X.
|
|
Major = 5;
|
|
Minor = 0;
|
|
Micro = 0;
|
|
break;
|
|
case IOS:
|
|
getOSVersion(Major, Minor, Micro);
|
|
// Default to 5.0 (or 7.0 for arm64).
|
|
if (Major == 0)
|
|
Major = (getArch() == aarch64) ? 7 : 5;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void Triple::setTriple(const Twine &Str) {
|
|
*this = Triple(Str);
|
|
}
|
|
|
|
void Triple::setArch(ArchType Kind) {
|
|
setArchName(getArchTypeName(Kind));
|
|
}
|
|
|
|
void Triple::setVendor(VendorType Kind) {
|
|
setVendorName(getVendorTypeName(Kind));
|
|
}
|
|
|
|
void Triple::setOS(OSType Kind) {
|
|
setOSName(getOSTypeName(Kind));
|
|
}
|
|
|
|
void Triple::setEnvironment(EnvironmentType Kind) {
|
|
if (ObjectFormat == getDefaultFormat(*this))
|
|
return setEnvironmentName(getEnvironmentTypeName(Kind));
|
|
|
|
setEnvironmentName((getEnvironmentTypeName(Kind) + Twine("-") +
|
|
getObjectFormatTypeName(ObjectFormat)).str());
|
|
}
|
|
|
|
void Triple::setObjectFormat(ObjectFormatType Kind) {
|
|
if (Environment == UnknownEnvironment)
|
|
return setEnvironmentName(getObjectFormatTypeName(Kind));
|
|
|
|
setEnvironmentName((getEnvironmentTypeName(Environment) + Twine("-") +
|
|
getObjectFormatTypeName(Kind)).str());
|
|
}
|
|
|
|
void Triple::setArchName(StringRef Str) {
|
|
// Work around a miscompilation bug for Twines in gcc 4.0.3.
|
|
SmallString<64> Triple;
|
|
Triple += Str;
|
|
Triple += "-";
|
|
Triple += getVendorName();
|
|
Triple += "-";
|
|
Triple += getOSAndEnvironmentName();
|
|
setTriple(Triple);
|
|
}
|
|
|
|
void Triple::setVendorName(StringRef Str) {
|
|
setTriple(getArchName() + "-" + Str + "-" + getOSAndEnvironmentName());
|
|
}
|
|
|
|
void Triple::setOSName(StringRef Str) {
|
|
if (hasEnvironment())
|
|
setTriple(getArchName() + "-" + getVendorName() + "-" + Str +
|
|
"-" + getEnvironmentName());
|
|
else
|
|
setTriple(getArchName() + "-" + getVendorName() + "-" + Str);
|
|
}
|
|
|
|
void Triple::setEnvironmentName(StringRef Str) {
|
|
setTriple(getArchName() + "-" + getVendorName() + "-" + getOSName() +
|
|
"-" + Str);
|
|
}
|
|
|
|
void Triple::setOSAndEnvironmentName(StringRef Str) {
|
|
setTriple(getArchName() + "-" + getVendorName() + "-" + Str);
|
|
}
|
|
|
|
static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
|
|
switch (Arch) {
|
|
case llvm::Triple::UnknownArch:
|
|
return 0;
|
|
|
|
case llvm::Triple::msp430:
|
|
return 16;
|
|
|
|
case llvm::Triple::arm:
|
|
case llvm::Triple::armeb:
|
|
case llvm::Triple::hexagon:
|
|
case llvm::Triple::le32:
|
|
case llvm::Triple::mips:
|
|
case llvm::Triple::mipsel:
|
|
case llvm::Triple::nvptx:
|
|
case llvm::Triple::ppc:
|
|
case llvm::Triple::r600:
|
|
case llvm::Triple::sparc:
|
|
case llvm::Triple::tce:
|
|
case llvm::Triple::thumb:
|
|
case llvm::Triple::thumbeb:
|
|
case llvm::Triple::x86:
|
|
case llvm::Triple::xcore:
|
|
case llvm::Triple::amdil:
|
|
case llvm::Triple::hsail:
|
|
case llvm::Triple::spir:
|
|
case llvm::Triple::kalimba:
|
|
return 32;
|
|
|
|
case llvm::Triple::aarch64:
|
|
case llvm::Triple::aarch64_be:
|
|
case llvm::Triple::amdgcn:
|
|
case llvm::Triple::bpf:
|
|
case llvm::Triple::le64:
|
|
case llvm::Triple::mips64:
|
|
case llvm::Triple::mips64el:
|
|
case llvm::Triple::nvptx64:
|
|
case llvm::Triple::ppc64:
|
|
case llvm::Triple::ppc64le:
|
|
case llvm::Triple::sparcv9:
|
|
case llvm::Triple::systemz:
|
|
case llvm::Triple::x86_64:
|
|
case llvm::Triple::amdil64:
|
|
case llvm::Triple::hsail64:
|
|
case llvm::Triple::spir64:
|
|
return 64;
|
|
}
|
|
llvm_unreachable("Invalid architecture value");
|
|
}
|
|
|
|
bool Triple::isArch64Bit() const {
|
|
return getArchPointerBitWidth(getArch()) == 64;
|
|
}
|
|
|
|
bool Triple::isArch32Bit() const {
|
|
return getArchPointerBitWidth(getArch()) == 32;
|
|
}
|
|
|
|
bool Triple::isArch16Bit() const {
|
|
return getArchPointerBitWidth(getArch()) == 16;
|
|
}
|
|
|
|
Triple Triple::get32BitArchVariant() const {
|
|
Triple T(*this);
|
|
switch (getArch()) {
|
|
case Triple::UnknownArch:
|
|
case Triple::aarch64:
|
|
case Triple::aarch64_be:
|
|
case Triple::amdgcn:
|
|
case Triple::bpf:
|
|
case Triple::msp430:
|
|
case Triple::systemz:
|
|
case Triple::ppc64le:
|
|
T.setArch(UnknownArch);
|
|
break;
|
|
|
|
case Triple::amdil:
|
|
case Triple::hsail:
|
|
case Triple::spir:
|
|
case Triple::arm:
|
|
case Triple::armeb:
|
|
case Triple::hexagon:
|
|
case Triple::kalimba:
|
|
case Triple::le32:
|
|
case Triple::mips:
|
|
case Triple::mipsel:
|
|
case Triple::nvptx:
|
|
case Triple::ppc:
|
|
case Triple::r600:
|
|
case Triple::sparc:
|
|
case Triple::tce:
|
|
case Triple::thumb:
|
|
case Triple::thumbeb:
|
|
case Triple::x86:
|
|
case Triple::xcore:
|
|
// Already 32-bit.
|
|
break;
|
|
|
|
case Triple::le64: T.setArch(Triple::le32); break;
|
|
case Triple::mips64: T.setArch(Triple::mips); break;
|
|
case Triple::mips64el: T.setArch(Triple::mipsel); break;
|
|
case Triple::nvptx64: T.setArch(Triple::nvptx); break;
|
|
case Triple::ppc64: T.setArch(Triple::ppc); break;
|
|
case Triple::sparcv9: T.setArch(Triple::sparc); break;
|
|
case Triple::x86_64: T.setArch(Triple::x86); break;
|
|
case Triple::amdil64: T.setArch(Triple::amdil); break;
|
|
case Triple::hsail64: T.setArch(Triple::hsail); break;
|
|
case Triple::spir64: T.setArch(Triple::spir); break;
|
|
}
|
|
return T;
|
|
}
|
|
|
|
Triple Triple::get64BitArchVariant() const {
|
|
Triple T(*this);
|
|
switch (getArch()) {
|
|
case Triple::UnknownArch:
|
|
case Triple::arm:
|
|
case Triple::armeb:
|
|
case Triple::hexagon:
|
|
case Triple::kalimba:
|
|
case Triple::msp430:
|
|
case Triple::r600:
|
|
case Triple::tce:
|
|
case Triple::thumb:
|
|
case Triple::thumbeb:
|
|
case Triple::xcore:
|
|
T.setArch(UnknownArch);
|
|
break;
|
|
|
|
case Triple::aarch64:
|
|
case Triple::aarch64_be:
|
|
case Triple::bpf:
|
|
case Triple::le64:
|
|
case Triple::amdil64:
|
|
case Triple::amdgcn:
|
|
case Triple::hsail64:
|
|
case Triple::spir64:
|
|
case Triple::mips64:
|
|
case Triple::mips64el:
|
|
case Triple::nvptx64:
|
|
case Triple::ppc64:
|
|
case Triple::ppc64le:
|
|
case Triple::sparcv9:
|
|
case Triple::systemz:
|
|
case Triple::x86_64:
|
|
// Already 64-bit.
|
|
break;
|
|
|
|
case Triple::le32: T.setArch(Triple::le64); break;
|
|
case Triple::mips: T.setArch(Triple::mips64); break;
|
|
case Triple::mipsel: T.setArch(Triple::mips64el); break;
|
|
case Triple::nvptx: T.setArch(Triple::nvptx64); break;
|
|
case Triple::ppc: T.setArch(Triple::ppc64); break;
|
|
case Triple::sparc: T.setArch(Triple::sparcv9); break;
|
|
case Triple::x86: T.setArch(Triple::x86_64); break;
|
|
case Triple::amdil: T.setArch(Triple::amdil64); break;
|
|
case Triple::hsail: T.setArch(Triple::hsail64); break;
|
|
case Triple::spir: T.setArch(Triple::spir64); break;
|
|
}
|
|
return T;
|
|
}
|
|
|
|
// FIXME: tblgen this.
|
|
const char *Triple::getARMCPUForArch(StringRef MArch) const {
|
|
if (MArch.empty())
|
|
MArch = getArchName();
|
|
|
|
switch (getOS()) {
|
|
case llvm::Triple::FreeBSD:
|
|
case llvm::Triple::NetBSD:
|
|
if (MArch == "armv6")
|
|
return "arm1176jzf-s";
|
|
break;
|
|
case llvm::Triple::Win32:
|
|
// FIXME: this is invalid for WindowsCE
|
|
return "cortex-a9";
|
|
default:
|
|
break;
|
|
}
|
|
|
|
const char *result = nullptr;
|
|
size_t offset = StringRef::npos;
|
|
if (MArch.startswith("arm"))
|
|
offset = 3;
|
|
if (MArch.startswith("thumb"))
|
|
offset = 5;
|
|
if (offset != StringRef::npos && MArch.substr(offset, 2) == "eb")
|
|
offset += 2;
|
|
if (MArch.endswith("eb"))
|
|
MArch = MArch.substr(0, MArch.size() - 2);
|
|
if (offset != StringRef::npos)
|
|
result = llvm::StringSwitch<const char *>(MArch.substr(offset))
|
|
.Cases("v2", "v2a", "arm2")
|
|
.Case("v3", "arm6")
|
|
.Case("v3m", "arm7m")
|
|
.Case("v4", "strongarm")
|
|
.Case("v4t", "arm7tdmi")
|
|
.Cases("v5", "v5t", "arm10tdmi")
|
|
.Cases("v5e", "v5te", "arm1022e")
|
|
.Case("v5tej", "arm926ej-s")
|
|
.Case("v6", "arm1136jf-s")
|
|
.Case("v6j", "arm1136j-s")
|
|
.Cases("v6k", "v6z", "v6zk", "arm1176jzf-s")
|
|
.Case("v6t2", "arm1156t2-s")
|
|
.Cases("v6m", "v6-m", "v6sm", "v6s-m", "cortex-m0")
|
|
.Cases("v7", "v7a", "v7-a", "v7l", "v7-l", "cortex-a8")
|
|
.Cases("v7s", "v7-s", "swift")
|
|
.Cases("v7r", "v7-r", "cortex-r4")
|
|
.Cases("v7m", "v7-m", "cortex-m3")
|
|
.Cases("v7em", "v7e-m", "cortex-m4")
|
|
.Cases("v8", "v8a", "v8-a", "cortex-a53")
|
|
.Cases("v8.1a", "v8.1-a", "generic-armv8.1-a")
|
|
.Default(nullptr);
|
|
else
|
|
result = llvm::StringSwitch<const char *>(MArch)
|
|
.Case("ep9312", "ep9312")
|
|
.Case("iwmmxt", "iwmmxt")
|
|
.Case("xscale", "xscale")
|
|
.Default(nullptr);
|
|
|
|
if (result)
|
|
return result;
|
|
|
|
// If all else failed, return the most base CPU with thumb interworking
|
|
// supported by LLVM.
|
|
// FIXME: Should warn once that we're falling back.
|
|
switch (getOS()) {
|
|
case llvm::Triple::NetBSD:
|
|
switch (getEnvironment()) {
|
|
case llvm::Triple::GNUEABIHF:
|
|
case llvm::Triple::GNUEABI:
|
|
case llvm::Triple::EABIHF:
|
|
case llvm::Triple::EABI:
|
|
return "arm926ej-s";
|
|
default:
|
|
return "strongarm";
|
|
}
|
|
case llvm::Triple::NaCl:
|
|
return "cortex-a8";
|
|
default:
|
|
switch (getEnvironment()) {
|
|
case llvm::Triple::EABIHF:
|
|
case llvm::Triple::GNUEABIHF:
|
|
return "arm1176jzf-s";
|
|
default:
|
|
return "arm7tdmi";
|
|
}
|
|
}
|
|
}
|