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subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
109 lines
4.4 KiB
C++
109 lines
4.4 KiB
C++
//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the classes used to describe a subtarget's machine model
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// for scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCSCHEDMODEL_H
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#define LLVM_MC_MCSCHEDMODEL_H
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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struct InstrItinerary;
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/// Machine model for scheduling, bundling, and heuristics.
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///
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/// The machine model directly provides basic information about the
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/// microarchitecture to the scheduler in the form of properties. It also
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/// optionally refers to scheduler resources tables and itinerary
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/// tables. Scheduler resources tables model the latency and cost for each
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/// instruction type. Itinerary tables are an independant mechanism that
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/// provides a detailed reservation table describing each cycle of instruction
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/// execution. Subtargets may define any or all of the above categories of data
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/// depending on the type of CPU and selected scheduler.
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class MCSchedModel {
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public:
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static MCSchedModel DefaultSchedModel; // For unknown processors.
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// IssueWidth is the maximum number of instructions that may be scheduled in
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// the same per-cycle group.
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unsigned IssueWidth;
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static const unsigned DefaultIssueWidth = 1;
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// MinLatency is the minimum latency between a register write
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// followed by a data dependent read. This determines which
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// instructions may be scheduled in the same per-cycle group. This
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// is distinct from *expected* latency, which determines the likely
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// critical path but does not guarantee a pipeline
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// hazard. MinLatency can always be overridden by the number of
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// InstrStage cycles.
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//
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// (-1) Standard in-order processor.
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// Use InstrItinerary OperandCycles as MinLatency.
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// If no OperandCycles exist, then use the cycle of the last InstrStage.
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//
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// (0) Out-of-order processor, or in-order with bundled dependencies.
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// RAW dependencies may be dispatched in the same cycle.
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// Optional InstrItinerary OperandCycles provides expected latency.
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//
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// (>0) In-order processor with variable latencies.
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// Use the greater of this value or the cycle of the last InstrStage.
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// Optional InstrItinerary OperandCycles provides expected latency.
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// TODO: can't yet specify both min and expected latency per operand.
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int MinLatency;
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static const unsigned DefaultMinLatency = -1;
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// LoadLatency is the expected latency of load instructions.
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//
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// If MinLatency >= 0, this may be overriden for individual load opcodes by
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// InstrItinerary OperandCycles.
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unsigned LoadLatency;
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static const unsigned DefaultLoadLatency = 4;
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// HighLatency is the expected latency of "very high latency" operations.
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// See TargetInstrInfo::isHighLatencyDef().
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// By default, this is set to an arbitrarily high number of cycles
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// likely to have some impact on scheduling heuristics.
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// If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
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unsigned HighLatency;
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static const unsigned DefaultHighLatency = 10;
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private:
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// TODO: Add a reference to proc resource types and sched resource tables.
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// Instruction itinerary tables used by InstrItineraryData.
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friend class InstrItineraryData;
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const InstrItinerary *InstrItineraries;
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public:
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// Default's must be specified as static const literals so that tablegenerated
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// target code can use it in static initializers. The defaults need to be
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// initialized in this default ctor because some clients directly instantiate
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// MCSchedModel instead of using a generated itinerary.
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MCSchedModel(): IssueWidth(DefaultMinLatency),
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MinLatency(DefaultMinLatency),
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LoadLatency(DefaultLoadLatency),
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HighLatency(DefaultHighLatency),
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InstrItineraries(0) {}
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// Table-gen driven ctor.
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MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl,
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const InstrItinerary *ii):
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IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
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InstrItineraries(ii){}
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};
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} // End llvm namespace
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#endif
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