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llvm-6502/test/CodeGen/X86
History
Bill Wendling ae595dc9da Moved this option to the front-end. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56901 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-01 01:02:18 +00:00
..
2002-12-23-LocalRAProblem.ll
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2002-12-23-SubProblem.ll
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2003-08-03-CallArgLiveRanges.ll
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2003-08-23-DeadBlockTest.ll
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2003-11-03-GlobalBool.ll
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2004-02-12-Memcpy.ll
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2004-02-13-FrameReturnAddress.ll
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2004-02-14-InefficientStackPointer.ll
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2004-02-22-Casts.ll
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2004-03-30-Select-Max.ll
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2004-04-09-SameValueCoalescing.ll
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2004-04-13-FPCMOV-Crash.ll
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2004-06-10-StackifierCrash.ll
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2004-10-08-SelectSetCCFold.ll
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2005-01-17-CycleInDAG.ll
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2005-02-14-IllegalAssembler.ll
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2005-05-08-FPStackifierPHI.ll
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2006-01-19-ISelFoldingBug.ll
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2006-03-01-InstrSchedBug.ll
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2006-03-02-InstrSchedBug.ll
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2006-04-04-CrossBlockCrash.ll
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2006-04-27-ISelFoldingBug.ll
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2006-05-01-SchedCausingSpills.ll
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2006-05-02-InstrSched1.ll
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2006-05-02-InstrSched2.ll
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2006-05-08-CoalesceSubRegClass.ll
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2006-05-08-InstrSched.ll
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2006-05-11-InstrSched.ll
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2006-05-17-VectorArg.ll
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2006-05-22-FPSetEQ.ll
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2006-05-25-CycleInDAG.ll
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2006-07-10-InlineAsmAConstraint.ll
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2006-07-12-InlineAsmQConstraint.ll
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2006-07-19-ATTAsm.ll
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2006-07-20-InlineAsm.ll
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2006-07-28-AsmPrint-Long-As-Pointer.ll
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2006-07-31-SingleRegClass.ll
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2006-08-07-CycleInDAG.ll
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2006-08-16-CycleInDAG.ll
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2006-08-21-ExtraMovInst.ll
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2006-09-01-CycleInDAG.ll
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2006-10-02-BoolRetCrash.ll
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2006-10-07-ScalarSSEMiscompile.ll
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2006-10-09-CycleInDAG.ll
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2006-10-10-FindModifiedNodeSlotBug.ll
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2006-10-12-CycleInDAG.ll
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2006-10-13-CycleInDAG.ll
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2006-10-19-SwitchUnnecessaryBranching.ll
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2006-11-12-CSRetCC.ll
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2006-11-17-IllegalMove.ll
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2006-11-27-SelectLegalize.ll
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2006-11-28-Memcpy.ll
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2006-12-19-IntelSyntax.ll
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2007-01-08-InstrSched.ll
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2007-01-13-StackPtrIndex.ll
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2007-01-29-InlineAsm-ir.ll
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2007-02-04-OrAddrMode.ll
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2007-02-19-LiveIntervalAssert.ll
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2007-02-25-FastCCStack.ll
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2007-03-01-SpillerCrash.ll
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2007-03-15-GEP-Idx-Sink.ll
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2007-03-16-InlineAsm.ll
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2007-03-18-LiveIntervalAssert.ll
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2007-03-24-InlineAsmMultiRegConstraint.ll
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2007-03-24-InlineAsmPModifier.ll
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2007-03-24-InlineAsmVectorOp.ll
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2007-03-24-InlineAsmXConstraint.ll
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2007-03-26-CoalescerBug.ll
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2007-04-08-InlineAsmCrash.ll
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2007-04-11-InlineAsmVectorResult.ll
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2007-04-17-LiveIntervalAssert.ll
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2007-04-24-Huge-Stack.ll
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2007-04-24-VectorCrash.ll
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2007-04-25-MMX-PADDQ.ll
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2007-04-27-InlineAsm-IntMemInput.ll
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2007-05-05-VecCastExpand.ll
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2007-05-07-InvokeSRet.ll
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2007-05-14-LiveIntervalAssert.ll
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2007-05-15-maskmovq.ll
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2007-05-17-ShuffleISelBug.ll
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2007-06-04-tailmerge4.ll
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2007-06-04-X86-64-CtorAsmBugs.ll
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2007-06-05-LSR-Dominator.ll
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2007-06-14-branchfold.ll
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2007-06-15-IntToMMX.ll
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2007-06-28-X86-64-isel.ll
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2007-06-29-DAGCombinerBug.ll
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2007-06-29-VecFPConstantCSEBug.ll
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2007-07-03-GR64ToVR64.ll
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2007-07-10-StackerAssert.ll
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2007-07-18-Vector-Extract.ll
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2007-08-01-LiveVariablesBug.ll
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2007-08-09-IllegalX86-64Asm.ll
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2007-08-10-SignExtSubreg.ll
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2007-08-13-AppendingLinkage.ll
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2007-08-13-SpillerReuse.ll
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
2008-09-04 22:59:58 +00:00
2007-09-03-X86-64-EhSelector.ll
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2007-09-05-InvalidAsm.ll
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2007-09-06-ExtWeakAliasee.ll
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2007-09-17-ObjcFrameEH.ll
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2007-09-18-ShuffleXformBug.ll
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2007-09-27-LDIntrinsics.ll
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2007-10-04-AvoidEFLAGSCopy.ll
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2007-10-05-3AddrConvert.ll
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2007-10-12-CoalesceExtSubReg.ll
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2007-10-12-SpillerUnfold1.ll
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2007-10-12-SpillerUnfold2.ll
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2007-10-14-CoalescerCrash.ll
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2007-10-15-CoalescerCrash.ll
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2007-10-16-CoalescerCrash.ll
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2007-10-16-fp80_select.ll
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2007-10-16-IllegalAsm.ll
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2007-10-17-IllegalAsm.ll
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2007-10-19-SpillerUnfold.ll
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2007-10-28-inlineasm-q-modifier.ll
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2007-10-29-ExtendSetCC.ll
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2007-10-30-LSRCrash.ll
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2007-10-31-extractelement-i64.ll
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2007-11-01-ISelCrash.ll
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2007-11-02-BadAsm.ll
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2007-11-03-x86-64-q-constraint.ll
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2007-11-04-LiveIntervalCrash.ll
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2007-11-04-LiveVariablesBug.ll
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2007-11-04-rip-immediate-constant.ll
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2007-11-06-InstrSched.ll
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2007-11-07-MulBy4.ll
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2007-11-14-Coalescer-Bug.ll
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2007-11-30-LoadFolding-Bug.ll
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2007-11-30-TestLoadFolding.ll
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2007-12-11-FoldImpDefSpill.ll
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2007-12-16-BURRSchedCrash.ll
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2007-12-18-LoadCSEBug.ll
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2008-01-08-IllegalCMP.ll
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2008-01-08-SchedulerCrash.ll
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2008-01-09-LongDoubleSin.ll
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2008-01-16-FPStackifierAssert.ll
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2008-01-16-InvalidDAGCombineXform.ll
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2008-01-16-Trampoline.ll
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2008-01-25-EmptyFunction.ll
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2008-02-05-ISelCrash.ll
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2008-02-06-LoadFoldingBug.ll
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2008-02-08-LoadFoldingBug.ll
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2008-02-14-BitMiscompile.ll
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2008-02-18-TailMergingBug.ll
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2008-02-20-InlineAsmClobber.ll
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2008-02-22-LocalRegAllocBug.ll
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2008-02-22-ReMatBug.ll
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
2008-09-04 22:59:58 +00:00
2008-02-25-InlineAsmBug.ll
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2008-02-25-X86-64-CoalescerBug.ll
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2008-02-26-AsmDirectMemOp.ll
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2008-02-27-DeadSlotElimBug.ll
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2008-02-27-PEICrash.ll
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2008-03-06-frem-fpstack.ll
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2008-03-07-APIntBug.ll
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2008-03-10-RegAllocInfLoop.ll
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2008-03-12-ThreadLocalAlias.ll
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2008-03-13-TwoAddrPassCrash.ll
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2008-03-14-SpillerCrash.ll
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2008-03-18-CoalescerBug.ll
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2008-03-19-DAGCombinerBug.ll
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2008-03-23-DarwinAsmComments.ll
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2008-03-25-TwoAddrPassBug.ll
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2008-03-31-SpillerFoldingBug.ll
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2008-04-02-unnamedEH.ll
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2008-04-08-CoalescerCrash.ll
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2008-04-09-BranchFolding.ll
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2008-04-15-LiveVariableBug.ll
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2008-04-16-CoalescerBug.ll
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2008-04-16-ReMatBug.ll
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2008-04-17-CoalescerBug.ll
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2008-04-24-MemCpyBug.ll
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2008-04-24-pblendw-fold-crash.ll
Loosen up an assertion to allow intrinsics. I really have no
2008-04-25 05:13:01 +00:00
2008-04-26-Asm-Optimize-Imm.ll
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2008-04-28-CoalescerBug.ll
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2008-04-28-CyclicSchedUnit.ll
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2008-05-01-InvalidOrdCompare.ll
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2008-05-06-SpillerBug.ll
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2008-05-09-PHIElimBug.ll
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2008-05-09-ShuffleLoweringBug.ll
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2008-05-12-tailmerge-5.ll
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2008-05-21-CoalescerBug.ll
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2008-05-22-FoldUnalignedLoad.ll
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2008-05-28-CoalescerBug.ll
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2008-05-28-LocalRegAllocBug.ll
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2008-06-04-MemCpyLoweringBug.ll
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2008-06-13-NotVolatileLoadStore.ll
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2008-06-13-VolatileLoadStore.ll
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2008-06-16-SubregsBug.ll
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2008-06-18-BadShuffle.ll
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2008-06-25-VecISelBug.ll
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2008-07-07-DanglingDeadInsts.ll
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2008-07-09-ELFSectionAttributes.ll
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2008-07-11-SHLBy1.ll
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2008-07-11-SpillerBug.ll
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2008-07-16-CoalescerCrash.ll
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2008-07-19-movups-spills.ll
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2008-07-22-CombinerCrash.ll
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2008-07-23-VSetCC.ll
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2008-08-05-SpillerBug.ll
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2008-08-06-RewriterBug.ll
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2008-08-17-UComiCodeGenBug.ll
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2008-08-19-SubAndFetch.ll
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2008-08-23-64Bit-maskmovq.ll
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2008-08-23-X86-64AsmBug.ll
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2008-08-25-AsmRegTypeMismatch.ll
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2008-08-31-EH_RETURN32.ll
Avoid spilling EBP / RBP twice in the prologue.
2008-09-26 19:14:21 +00:00
2008-08-31-EH_RETURN64.ll
Avoid spilling EBP / RBP twice in the prologue.
2008-09-26 19:14:21 +00:00
2008-09-05-sinttofp-2xi32.ll
Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x
2008-09-05 23:07:03 +00:00
2008-09-09-LinearScanBug.ll
Fix PR2757. Ignore liveinterval register allocation preference if the preference register is not in the right register class. This can happen due to sub-register coalescing.
2008-09-09 20:22:01 +00:00
2008-09-10-SpillerBug2.ll
Propagate subreg index when promoting a load to a copy.
2008-09-11 01:02:12 +00:00
2008-09-11-CoalescerBug2.ll
Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g.
2008-09-11 20:07:10 +00:00
2008-09-11-CoalescerBug.ll
Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check.
2008-09-11 18:40:32 +00:00
2008-09-17-inline-asm-1.ll
Remove SelectionDag early allocation of registers
2008-09-24 23:13:09 +00:00
2008-09-18-inline-asm-2.ll
Remove SelectionDag early allocation of registers
2008-09-24 23:13:09 +00:00
2008-09-19-RegAllocBug.ll
Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on.
2008-09-20 01:28:05 +00:00
2008-09-25-sseregparm-1.ll
Accept 'inreg' attribute on x86 functions as
2008-09-25 20:47:45 +00:00
2008-09-26-FrameAddrBug.ll
Re-apply 56683 with fixes.
2008-09-27 01:56:22 +00:00
2008-09-29-ReMatBug.ll
Re-apply 56835 along with header file changes.
2008-09-30 15:44:16 +00:00
2008-09-29-VolatileBug.ll
Fix PR2835. Do not change the width of a volatile load.
2008-09-29 17:26:18 +00:00
aliases.ll
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aligned-comm.ll
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all-ones-vector.ll
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alloca-align-rounding.ll
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and-or-fold.ll
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arg-cast.ll
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asm-block-labels.ll
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asm-global-imm.ll
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asm-indirect-mem.ll
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atomic_op.ll
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Atomics-32.ll
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Atomics-64.ll
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bitcast2.ll
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bitcast-int-to-vector.ll
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bitcast.ll
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bswap.ll
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byval2.ll
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byval3.ll
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byval4.ll
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byval5.ll
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byval6.ll
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byval7.ll
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byval.ll
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call-push.ll
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clz.ll
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cmp0.ll
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cmp1.ll
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cmp2.ll
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cmp-test.ll
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coalescer-commute1.ll
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coalescer-commute2.ll
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coalescer-commute3.ll
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
2008-09-04 22:59:58 +00:00
coalescer-commute4.ll
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coalescer-commute5.ll
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coalescer-remat.ll
Re-materalized definition instructions may be dead. Whack them.
2008-09-19 17:38:47 +00:00
combine-lds.ll
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
2008-09-04 22:59:58 +00:00
commute-intrinsic.ll
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commute-two-addr.ll
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compare_folding.ll
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compare-add.ll
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constant-pool-remat-0.ll
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls.
2008-09-05 17:24:07 +00:00
copysign-zero.ll
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dagcombine-cse.ll
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darwin-bzero.ll
Moved this option to the front-end.
2008-10-01 01:02:18 +00:00
darwin-no-dead-strip.ll
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darwin-stub.ll
No need to print function stubs for Mac OS X 10.5 and up. Linker will handle it.
2008-09-20 00:13:45 +00:00
dg.exp
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div_const.ll
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divrem.ll
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dollar-name.ll
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dyn-stackalloc.ll
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epilogue.ll
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extend.ll
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extern_weak.ll
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extmul64.ll
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extmul128.ll
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extractelement-from-arg.ll
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extractelement-load.ll
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extractps.ll
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fabs.ll
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fast-cc-callee-pops.ll
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fast-cc-merge-stack-adj.ll
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fast-cc-pass-in-regs.ll
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fast-isel-call.ll
Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit.
2008-09-08 17:15:42 +00:00
fast-isel-mem.ll
Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
2008-09-19 22:16:54 +00:00
fast-isel-phys.ll
Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs.
2008-09-08 08:39:33 +00:00
fast-isel-trunc.ll
Handle x86 truncate to i8 with target hook for now.
2008-09-07 08:47:42 +00:00
fast-isel.ll
Load from GV stub should be locally CSE'd.
2008-09-04 06:18:33 +00:00
fastcall-correct-mangling.ll
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fastcc-2.ll
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls.
2008-09-05 17:24:07 +00:00
fastcc-sret.ll
Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc.
2008-09-10 18:25:29 +00:00
fastcc.ll
Fix test.
2008-09-05 20:04:37 +00:00
field-extract-use-trunc.ll
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fildll.ll
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fold-and-shift.ll
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fold-call-2.ll
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fold-call.ll
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fold-load.ll
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fold-mul-lohi.ll
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fp2sint.ll
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fp_constant_op.ll
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fp_load_cast_fold.ll
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fp_load_fold.ll
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fp-immediate-shorten.ll
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fp-in-intregs.ll
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fp-stack-2results.ll
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fp-stack-compare.ll
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fp-stack-direct-ret.ll
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fp-stack-ret-conv.ll
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fp-stack-ret-store.ll
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fp-stack-ret.ll
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fp-stack-retcopy.ll
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fsxor-alignment.ll
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hidden-vis.ll
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i128-immediate.ll
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i128-mul.ll
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i128-ret.ll
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iabs.ll
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illegal-insert.ll
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illegal-vector-args-return.ll
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imp-def-copies.ll
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imul-lea.ll
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inline-asm-fpstack.ll
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inline-asm-mrv.ll
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inline-asm-pic.ll
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
2008-09-24 00:05:32 +00:00
inline-asm-x-scalar.ll
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inline-asm.ll
Support x86 specific inline asm modifier 'J'.
2008-09-22 23:57:37 +00:00
ins_subreg_coalesce-1.ll
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ins_subreg_coalesce-2.ll
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ins_subreg_coalesce-3.ll
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insertelement-copytoregs.ll
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invalid-shift-immediate.ll
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isel-sink.ll
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isnan2.ll
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isnan.ll
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ispositive.ll
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jump_sign.ll
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ldzero.ll
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lea-2.ll
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lea-3.ll
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lea-recursion.ll
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lea.ll
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lfence.ll
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long-setcc.ll
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longlong-deadload.ll
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loop-hoist.ll
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loop-strength-reduce2.ll
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loop-strength-reduce3.ll
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loop-strength-reduce4.ll
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loop-strength-reduce5.ll
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loop-strength-reduce6.ll
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loop-strength-reduce.ll
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lsr-negative-stride.ll
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memcpy-2.ll
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memcpy.ll
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memmove-0.ll
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memmove-1.ll
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memmove-2.ll
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memmove-3.ll
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memmove-4.ll
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memset64-on-x86-32.ll
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memset-2.ll
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memset.ll
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mfence.ll
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mingw-alloca.ll
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mmx-arg-passing2.ll
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mmx-arg-passing.ll
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mmx-arith.ll
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mmx-bitcast-to-i64.ll
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mmx-copy-gprs.ll
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mmx-emms.ll
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mmx-insert-element.ll
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mmx-pinsrw.ll
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mmx-punpckhdq.ll
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mmx-s2v.ll
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mmx-shift.ll
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mmx-shuffle.ll
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mul64.ll
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mul128.ll
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mul-legalize.ll
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mul-remat.ll
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mul-shift-reassoc.ll
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multiple-return-values-cross-block.ll
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multiple-return-values.ll
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nancvt.ll
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negative_zero.ll
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negative-sin.ll
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nofence.ll
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opt-ext-uses.ll
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optimize-smax.ll
Teach LSR to optimize away SMAX operations for tripcounts in common
2008-09-15 21:22:06 +00:00
or-branch.ll
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overlap-shift.ll
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packed_struct.ll
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peep-vector-extract-concat.ll
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peep-vector-extract-insert.ll
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pic_jumptable.ll
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pic-1.ll
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pic-2.ll
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pic-3.ll
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pic-4.ll
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pic-5.ll
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pic-6.ll
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pic-cpool.ll
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pic-jtbl.ll
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pic-load-remat.ll
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pmul.ll
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postalloc-coalescing.ll
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pr1462.ll
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pr1489.ll
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pr1505.ll
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pr1505b.ll
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pr2177.ll
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pr2182.ll
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pr2326.ll
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pr2623.ll
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pr2656.ll
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prefetch.ll
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rdtsc.ll
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regpressure.ll
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rem.ll
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remat-constant.ll
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remat-mov0.ll
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rotate2.ll
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rotate.ll
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scalar_sse_minmax.ll
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scalar-min-max-fill-operand.ll
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select-zero-one.ll
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select.ll
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setuge.ll
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sext-load.ll
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sext-select.ll
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sext-trunc.ll
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sfence.ll
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shift-and.ll
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shift-coalesce.ll
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shift-codegen.ll
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shift-combine.ll
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shift-double.ll
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shift-folding.ll
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shift-one.ll
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shl_elim.ll
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shrink-fp-const1.ll
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shrink-fp-const2.ll
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sincos.ll
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small-byval-memcpy.ll
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split-select.ll
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split-vector-rem.ll
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sret.ll
Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc.
2008-09-10 18:25:29 +00:00
sse41-extractps-bitcast-0.ll
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sse41-extractps-bitcast-1.ll
…
sse41-pmovx.ll
Use explicit target-triples to unbreak this test on non-darwin systems.
2008-10-01 00:25:38 +00:00
sse_reload_fold.ll
…
sse-align-0.ll
…
sse-align-1.ll
…
sse-align-2.ll
…
sse-align-3.ll
…
sse-align-4.ll
…
sse-align-5.ll
…
sse-align-6.ll
…
sse-align-7.ll
…
sse-align-8.ll
…
sse-align-9.ll
…
sse-align-10.ll
…
sse-align-11.ll
…
sse-align-12.ll
…
sse-fcopysign.ll
…
sse-load-ret.ll
…
sse-varargs.ll
…
stack-align.ll
…
store_op_load_fold2.ll
…
store_op_load_fold.ll
…
store-fp-constant.ll
…
store-global-address.ll
…
storetrunc-fp.ll
…
stride-nine-with-base-reg.ll
…
stride-reuse.ll
…
subclass-coalesce.ll
…
subreg-to-reg-0.ll
…
subreg-to-reg-1.ll
…
tailcall1.ll
…
tailcall-stackalign.ll
Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
2008-09-22 14:50:07 +00:00
tailcallbyval64.ll
…
tailcallbyval.ll
Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
2008-09-22 14:50:07 +00:00
tailcallfp2.ll
Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
2008-09-22 14:50:07 +00:00
tailcallfp.ll
Add indirect tail call (function pointer) examples.
2008-09-11 22:24:28 +00:00
tailcallpic1.ll
…
tailcallpic2.ll
…
tailcallstack64.ll
…
test-nofold.ll
…
tls1.ll
…
tls2.ll
…
trap.ll
…
trunc-to-bool.ll
…
twoaddr-pass-sink.ll
…
twoaddr-remat.ll
…
uint_to_fp.ll
…
urem-i8-constant.ll
…
v4f32-immediate.ll
…
variable-sized-darwin-bzero.ll
…
variadic-node-pic.ll
…
vec_add.ll
…
vec_align.ll
…
vec_call.ll
…
vec_clear.ll
…
vec_ctbits.ll
…
vec_extract-sse4.ll
…
vec_extract.ll
Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size.
2008-09-26 23:41:32 +00:00
vec_fneg.ll
…
vec_ins_extract.ll
…
vec_insert_4.ll
…
vec_insert-2.ll
…
vec_insert-3.ll
…
vec_insert-5.ll
…
vec_insert-6.ll
…
vec_insert-7.ll
…
vec_insert.ll
…
vec_loadhl.ll
…
vec_logical.ll
…
vec_return.ll
…
vec_select.ll
…
vec_set-2.ll
…
vec_set-3.ll
…
vec_set-4.ll
…
vec_set-5.ll
…
vec_set-6.ll
…
vec_set-7.ll
…
vec_set-8.ll
…
vec_set-9.ll
Prefer movlhps over punpcklqdq, etc. in more cases.
2008-09-25 23:35:16 +00:00
vec_set-A.ll
…
vec_set-B.ll
…
vec_set-C.ll
…
vec_set-D.ll
…
vec_set-E.ll
…
vec_set-F.ll
…
vec_set-G.ll
…
vec_set-H.ll
…
vec_set-I.ll
…
vec_set-J.ll
…
vec_set.ll
…
vec_shift2.ll
…
vec_shift3.ll
…
vec_shift.ll
…
vec_shuffle-2.ll
…
vec_shuffle-3.ll
…
vec_shuffle-4.ll
…
vec_shuffle-5.ll
…
vec_shuffle-6.ll
…
vec_shuffle-7.ll
…
vec_shuffle-8.ll
…
vec_shuffle-9.ll
…
vec_shuffle-10.ll
…
vec_shuffle-11.ll
…
vec_shuffle-12.ll
…
vec_shuffle-13.ll
…
vec_shuffle-14.ll
…
vec_shuffle-15.ll
…
vec_shuffle-16.ll
…
vec_shuffle-17.ll
…
vec_shuffle-18.ll
…
vec_shuffle-19.ll
…
vec_shuffle-20.ll
…
vec_shuffle-21.ll
…
vec_shuffle-22.ll
With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps
2008-09-25 20:50:48 +00:00
vec_shuffle-23.ll
Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size.
2008-09-26 23:41:32 +00:00
vec_shuffle.ll
…
vec_splat-2.ll
…
vec_splat.ll
…
vec_ss_load_fold.ll
…
vec_zero_cse.ll
…
vec_zero-2.ll
…
vec_zero.ll
…
vector-intrinsics.ll
…
vector-rem.ll
…
vector-variable-idx.ll
…
vector.ll
…
vfcmp.ll
…
vortex-bug.ll
…
weak.ll
…
x86-64-and-mask.ll
…
x86-64-arg.ll
…
x86-64-asm.ll
…
x86-64-dead-stack-adjust.ll
…
x86-64-frameaddr.ll
Re-apply 56683 with fixes.
2008-09-27 01:56:22 +00:00
x86-64-gv-offset.ll
…
x86-64-mem.ll
…
x86-64-pic-1.ll
…
x86-64-pic-2.ll
…
x86-64-pic-3.ll
…
x86-64-pic-4.ll
…
x86-64-pic-5.ll
…
x86-64-pic-6.ll
…
x86-64-pic-7.ll
…
x86-64-pic-8.ll
…
x86-64-pic-9.ll
…
x86-64-pic-10.ll
…
x86-64-pic-11.ll
…
x86-64-ret0.ll
…
x86-64-shortint.ll
…
x86-64-sret-return.ll
…
x86-64-varargs.ll
…
x86-frameaddr2.ll
Re-apply 56683 with fixes.
2008-09-27 01:56:22 +00:00
x86-frameaddr.ll
Re-apply 56683 with fixes.
2008-09-27 01:56:22 +00:00
xmm-r64.ll
…
xor_not.ll
…
xor-undef.ll
…
xorl.ll
…
zero-remat.ll
…
zext-inreg-0.ll
…
zext-inreg-1.ll
…