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7d24705f65
callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
965 B
LLVM
26 lines
965 B
LLVM
; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
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target triple = "thumbv7-apple-darwin10"
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; This tests the fast register allocator's handling of partial redefines:
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;
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; %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025...
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; %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill>
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;
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; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
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; redef, it cannot also get %Q0.
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; CHECK: vld1.64 {d16, d17}, [r{{.}}]
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; CHECK-NOT: vld1.64 {d16, d17}
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; CHECK: vmov.f64 d19, d16
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define i32 @test(i8* %arg) nounwind {
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entry:
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%0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg, i32 1)
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%1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2>
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store <2 x i64> %1, <2 x i64>* undef, align 16
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ret i32 undef
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}
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declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly
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