llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-02 22:32:08 +00:00

History

Brian Gaeke af0492ea52 Rename the load and store opcodes. The non-fp ones only have one

variant worth worrying about; the fp ones have two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14362 91177308-0d34-0410-b5e6-96231b3b80d8

2004-06-24 07:37:12 +00:00

DelaySlotFiller.cpp

JMPL has a delay slot.

2004-06-18 08:18:54 +00:00

InstSelectSimple.cpp

Rename the load and store opcodes. The non-fp ones only have one

2004-06-24 07:36:48 +00:00

Makefile

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README.txt

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SparcV8.h

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SparcV8.td

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SparcV8AsmPrinter.cpp

Rename the load and store opcodes. The non-fp ones only have one

2004-06-24 07:37:12 +00:00

SparcV8CodeEmitter.cpp

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SparcV8InstrInfo_F2.td

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SparcV8InstrInfo_F3.td

Clean up the commented-out F3_3 stuff.

2004-06-18 06:28:21 +00:00

SparcV8InstrInfo.cpp

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SparcV8InstrInfo.h

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SparcV8InstrInfo.td

Rename the load and store opcodes. The non-fp ones only have one

2004-06-24 07:36:59 +00:00

SparcV8ISelSimple.cpp

Rename the load and store opcodes. The non-fp ones only have one

2004-06-24 07:36:48 +00:00

SparcV8JITInfo.h

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SparcV8RegisterInfo.cpp

Rename the load and store opcodes. The non-fp ones only have one

2004-06-24 07:37:12 +00:00

SparcV8RegisterInfo.h

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SparcV8RegisterInfo.td

Add pseudo-registers and register class for 64-bit integer values.

2004-06-22 20:14:41 +00:00

SparcV8TargetMachine.cpp

Order #includes as per style guide.

2004-06-21 21:54:40 +00:00

SparcV8TargetMachine.h

Adjust to new TM interfaces

2004-06-02 05:47:26 +00:00

README.txt

SparcV8 backend skeleton
------------------------

This directory will house a 32-bit SPARC V8 backend employing a expander-based
instruction selector.  Watch this space for more news coming soon!

$Date$