Anton Korobeynikov f194b0edc9 Add testcase for register scanveger assertion fix in r72755 ...

(double def due to livevars)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73096 91177308-0d34-0410-b5e6-96231b3b80d8

2009-06-08 22:54:15 +00:00

..

Alpha

Fix Alpha test and support for private linkage.

2009-01-15 21:51:46 +00:00

ARM

Add testcase for register scanveger assertion fix in r72755

2009-06-08 22:54:15 +00:00

CBackend

Fix an erroneous check for isFNeg; the FNeg case is handled

2009-06-04 23:43:29 +00:00

CellSPU

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

CPP

Fix code emission for conditional branches.

2009-05-04 19:10:38 +00:00

Generic

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

IA64

…

Mips

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

MSP430

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

PowerPC

PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec

2009-06-07 01:07:55 +00:00

SPARC

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

X86

Fix the run-line for this test to work correctly outside of x86.

2009-06-07 09:44:19 +00:00

XCore

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00