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- No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75859 91177308-0d34-0410-b5e6-96231b3b80d8
106 lines
3.8 KiB
C++
106 lines
3.8 KiB
C++
//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC -----*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PowerPC specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PPC_TARGETMACHINE_H
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#define PPC_TARGETMACHINE_H
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#include "PPCFrameInfo.h"
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#include "PPCSubtarget.h"
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#include "PPCJITInfo.h"
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#include "PPCInstrInfo.h"
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#include "PPCISelLowering.h"
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#include "PPCMachOWriterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetData.h"
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namespace llvm {
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class PassManager;
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class GlobalValue;
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/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
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///
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class PPCTargetMachine : public LLVMTargetMachine {
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PPCSubtarget Subtarget;
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const TargetData DataLayout; // Calculates type size & alignment
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PPCInstrInfo InstrInfo;
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PPCFrameInfo FrameInfo;
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PPCJITInfo JITInfo;
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PPCTargetLowering TLInfo;
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InstrItineraryData InstrItins;
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PPCMachOWriterInfo MachOWriterInfo;
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protected:
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virtual const TargetAsmInfo *createTargetAsmInfo() const;
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public:
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PPCTargetMachine(const Target &T, const Module &M, const std::string &FS,
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bool is64Bit);
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virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
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virtual const PPCFrameInfo *getFrameInfo() const { return &FrameInfo; }
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virtual PPCJITInfo *getJITInfo() { return &JITInfo; }
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virtual PPCTargetLowering *getTargetLowering() const {
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return const_cast<PPCTargetLowering*>(&TLInfo);
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}
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virtual const PPCRegisterInfo *getRegisterInfo() const {
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return &InstrInfo.getRegisterInfo();
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}
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virtual const TargetData *getTargetData() const { return &DataLayout; }
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virtual const PPCSubtarget *getSubtargetImpl() const { return &Subtarget; }
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virtual const InstrItineraryData getInstrItineraryData() const {
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return InstrItins;
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}
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virtual const PPCMachOWriterInfo *getMachOWriterInfo() const {
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return &MachOWriterInfo;
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}
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// Pass Pipeline Configuration
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virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
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virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
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MachineCodeEmitter &MCE);
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virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE);
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virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
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ObjectCodeEmitter &OCE);
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virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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MachineCodeEmitter &MCE);
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virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE);
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virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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ObjectCodeEmitter &OCE);
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virtual bool getEnableTailMergeDefault() const;
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};
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/// PPC32TargetMachine - PowerPC 32-bit target machine.
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///
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class PPC32TargetMachine : public PPCTargetMachine {
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public:
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PPC32TargetMachine(const Target &T, const Module &M, const std::string &FS);
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};
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/// PPC64TargetMachine - PowerPC 64-bit target machine.
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///
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class PPC64TargetMachine : public PPCTargetMachine {
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public:
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PPC64TargetMachine(const Target &T, const Module &M, const std::string &FS);
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};
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} // end namespace llvm
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#endif
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