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This is disabled by default, but can be enabled with the subtarget feature: 'vgpr-spilling' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226597 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
1.9 KiB
C++
67 lines
1.9 KiB
C++
//===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
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#include "AMDGPUMachineFunction.h"
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#include "SIRegisterInfo.h"
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#include <map>
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namespace llvm {
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class MachineRegisterInfo;
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/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
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/// tells the hardware which interpolation parameters to load.
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class SIMachineFunctionInfo : public AMDGPUMachineFunction {
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void anchor() override;
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unsigned TIDReg;
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bool HasSpilledVGPRs;
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public:
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struct SpilledReg {
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unsigned VGPR;
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int Lane;
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SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
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SpilledReg() : VGPR(0), Lane(-1) { }
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bool hasLane() { return Lane != -1;}
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};
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// SIMachineFunctionInfo definition
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SIMachineFunctionInfo(const MachineFunction &MF);
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SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
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unsigned SubIdx);
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unsigned PSInputAddr;
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unsigned NumUserSGPRs;
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std::map<unsigned, unsigned> LaneVGPRs;
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unsigned LDSWaveSpillSize;
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unsigned ScratchOffsetReg;
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bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
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unsigned getTIDReg() const { return TIDReg; };
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void setTIDReg(unsigned Reg) { TIDReg = Reg; }
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bool hasSpilledVGPRs() const { return HasSpilledVGPRs; }
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void setHasSpilledVGPRs(bool Spill = true) { HasSpilledVGPRs = Spill; }
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unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
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};
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} // End namespace llvm
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#endif
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