Weiming Zhao 1c6611db44 Bug 18149: [AArch32] VSel instructions has no ARMCC field ...

The current peephole optimizing for compare inst assumes an instr that
uses CPSR has an MO for ARM Cond code.However, for VSEL instructions
(vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do
they support the modification of Cond Code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196588 91177308-0d34-0410-b5e6-96231b3b80d8

2013-12-06 17:56:48 +00:00

..

AArch64

For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64.

2013-12-05 02:12:01 +00:00

ARM

Bug 18149: [AArch32] VSel instructions has no ARMCC field

2013-12-06 17:56:48 +00:00

CPP

…

Generic

…

Hexagon

…

Inputs

…

Mips

[mips] Small code generation improvement for conditional operator (select)

2013-12-05 12:07:05 +00:00

MSP430

…

NVPTX

[NVPTX] Fix off-by-one error when creating the VT list for an SDNode

2013-12-05 12:58:00 +00:00

PowerPC

Correct word hyphenations

2013-12-05 05:44:44 +00:00

R600

R600/SI: Add comments for number of used registers.

2013-12-05 05:15:35 +00:00

SPARC

…

SystemZ

[SystemZ] Use LOAD AND TEST for comparisons with -0

2013-12-06 09:59:12 +00:00

Thumb

…

Thumb2

Add support for parsing ARM symbol variants on ELF targets

2013-12-04 22:43:20 +00:00

X86

Update AVX512 vector blend intrinsic names.

2013-12-06 13:35:35 +00:00

XCore

XCore target: Make handling of large frames not dependent upon an FP.

2013-12-02 11:05:28 +00:00