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information and update all callers. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
499 lines
14 KiB
C++
499 lines
14 KiB
C++
//===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a simple local pass that attempts to fill delay slots with useful
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// instructions. If no instructions can be moved into the delay slot, then a
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// NOP is placed.
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//===----------------------------------------------------------------------===//
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#include "Sparc.h"
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#include "SparcSubtarget.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "delay-slot-filler"
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STATISTIC(FilledSlots, "Number of delay slots filled");
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static cl::opt<bool> DisableDelaySlotFiller(
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"disable-sparc-delay-filler",
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cl::init(false),
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cl::desc("Disable the Sparc delay slot filler."),
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cl::Hidden);
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namespace {
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struct Filler : public MachineFunctionPass {
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/// Target machine description which we query for reg. names, data
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/// layout, etc.
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///
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TargetMachine &TM;
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const SparcSubtarget *Subtarget;
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static char ID;
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Filler(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm),
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Subtarget(&TM.getSubtarget<SparcSubtarget>()) {
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}
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const char *getPassName() const override {
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return "SPARC Delay Slot Filler";
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}
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F) override {
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bool Changed = false;
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// This pass invalidates liveness information when it reorders
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// instructions to fill delay slot.
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F.getRegInfo().invalidateLiveness();
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for (MachineFunction::iterator FI = F.begin(), FE = F.end();
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FI != FE; ++FI)
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Changed |= runOnMachineBasicBlock(*FI);
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return Changed;
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}
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void insertCallDefsUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegDefs,
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SmallSet<unsigned, 32>& RegUses);
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void insertDefsUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegDefs,
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SmallSet<unsigned, 32>& RegUses);
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bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
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unsigned Reg);
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bool delayHasHazard(MachineBasicBlock::iterator candidate,
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bool &sawLoad, bool &sawStore,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses);
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MachineBasicBlock::iterator
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findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
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bool needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize);
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bool tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI);
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};
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char Filler::ID = 0;
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} // end of anonymous namespace
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/// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
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/// slots in Sparc MachineFunctions
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///
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FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
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return new Filler(tm);
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}
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/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
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/// We assume there is only one delay slot per delayed instruction.
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///
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bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo();
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
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MachineBasicBlock::iterator MI = I;
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++I;
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// If MI is restore, try combining it with previous inst.
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if (!DisableDelaySlotFiller &&
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(MI->getOpcode() == SP::RESTORErr
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|| MI->getOpcode() == SP::RESTOREri)) {
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Changed |= tryCombineRestoreWithPrevInst(MBB, MI);
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continue;
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}
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if (!Subtarget->isV9() &&
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(MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
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|| MI->getOpcode() == SP::FCMPQ)) {
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BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
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Changed = true;
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continue;
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}
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// If MI has no delay slot, skip.
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if (!MI->hasDelaySlot())
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continue;
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MachineBasicBlock::iterator D = MBB.end();
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if (!DisableDelaySlotFiller)
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D = findDelayInstr(MBB, MI);
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++FilledSlots;
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Changed = true;
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if (D == MBB.end())
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BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
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else
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MBB.splice(I, &MBB, D);
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unsigned structSize = 0;
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if (needsUnimp(MI, structSize)) {
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MachineBasicBlock::iterator J = MI;
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++J; // skip the delay filler.
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assert (J != MBB.end() && "MI needs a delay instruction.");
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BuildMI(MBB, ++J, MI->getDebugLoc(),
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TII->get(SP::UNIMP)).addImm(structSize);
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// Bundle the delay filler and unimp with the instruction.
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MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), J);
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} else {
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MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), I);
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}
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}
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return Changed;
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}
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MachineBasicBlock::iterator
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Filler::findDelayInstr(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator slot)
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{
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SmallSet<unsigned, 32> RegDefs;
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SmallSet<unsigned, 32> RegUses;
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bool sawLoad = false;
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bool sawStore = false;
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if (slot == MBB.begin())
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return MBB.end();
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if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL)
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return MBB.end();
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if (slot->getOpcode() == SP::RETL) {
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MachineBasicBlock::iterator J = slot;
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--J;
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if (J->getOpcode() == SP::RESTORErr
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|| J->getOpcode() == SP::RESTOREri) {
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// change retl to ret.
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slot->setDesc(TM.getSubtargetImpl()->getInstrInfo()->get(SP::RET));
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return J;
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}
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}
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// Call's delay filler can def some of call's uses.
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if (slot->isCall())
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insertCallDefsUses(slot, RegDefs, RegUses);
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else
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insertDefsUses(slot, RegDefs, RegUses);
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bool done = false;
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MachineBasicBlock::iterator I = slot;
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while (!done) {
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done = (I == MBB.begin());
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if (!done)
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--I;
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// skip debug value
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if (I->isDebugValue())
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continue;
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if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
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I->hasDelaySlot() || I->isBundledWithSucc())
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break;
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if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
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insertDefsUses(I, RegDefs, RegUses);
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continue;
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}
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return I;
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}
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return MBB.end();
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}
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bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
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bool &sawLoad,
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bool &sawStore,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses)
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{
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if (candidate->isImplicitDef() || candidate->isKill())
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return true;
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if (candidate->mayLoad()) {
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sawLoad = true;
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if (sawStore)
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return true;
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}
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if (candidate->mayStore()) {
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if (sawStore)
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return true;
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sawStore = true;
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if (sawLoad)
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return true;
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}
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for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
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const MachineOperand &MO = candidate->getOperand(i);
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if (!MO.isReg())
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continue; // skip
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unsigned Reg = MO.getReg();
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if (MO.isDef()) {
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// check whether Reg is defined or used before delay slot.
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if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
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return true;
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}
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if (MO.isUse()) {
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// check whether Reg is defined before delay slot.
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if (IsRegInSet(RegDefs, Reg))
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return true;
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}
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}
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return false;
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}
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void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegDefs,
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SmallSet<unsigned, 32>& RegUses)
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{
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// Call defines o7, which is visible to the instruction in delay slot.
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RegDefs.insert(SP::O7);
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switch(MI->getOpcode()) {
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default: llvm_unreachable("Unknown opcode.");
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case SP::CALL: break;
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case SP::CALLrr:
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case SP::CALLri:
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assert(MI->getNumOperands() >= 2);
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const MachineOperand &Reg = MI->getOperand(0);
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assert(Reg.isReg() && "CALL first operand is not a register.");
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assert(Reg.isUse() && "CALL first operand is not a use.");
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RegUses.insert(Reg.getReg());
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const MachineOperand &RegOrImm = MI->getOperand(1);
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if (RegOrImm.isImm())
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break;
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assert(RegOrImm.isReg() && "CALLrr second operand is not a register.");
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assert(RegOrImm.isUse() && "CALLrr second operand is not a use.");
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RegUses.insert(RegOrImm.getReg());
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break;
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}
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}
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// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
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void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
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SmallSet<unsigned, 32>& RegDefs,
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SmallSet<unsigned, 32>& RegUses)
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{
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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continue;
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if (MO.isDef())
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RegDefs.insert(Reg);
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if (MO.isUse()) {
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// Implicit register uses of retl are return values and
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// retl does not use them.
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if (MO.isImplicit() && MI->getOpcode() == SP::RETL)
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continue;
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RegUses.insert(Reg);
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}
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}
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}
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// returns true if the Reg or its alias is in the RegSet.
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bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg)
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{
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// Check Reg and all aliased Registers.
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for (MCRegAliasIterator AI(Reg, TM.getSubtargetImpl()->getRegisterInfo(),
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true);
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AI.isValid(); ++AI)
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if (RegSet.count(*AI))
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return true;
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return false;
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}
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bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
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{
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if (!I->isCall())
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return false;
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unsigned structSizeOpNum = 0;
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switch (I->getOpcode()) {
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default: llvm_unreachable("Unknown call opcode.");
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case SP::CALL: structSizeOpNum = 1; break;
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case SP::CALLrr:
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case SP::CALLri: structSizeOpNum = 2; break;
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case SP::TLS_CALL: return false;
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}
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const MachineOperand &MO = I->getOperand(structSizeOpNum);
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if (!MO.isImm())
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return false;
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StructSize = MO.getImm();
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return true;
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}
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static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI,
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MachineBasicBlock::iterator AddMI,
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const TargetInstrInfo *TII)
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{
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// Before: add <op0>, <op1>, %i[0-7]
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// restore %g0, %g0, %i[0-7]
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//
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// After : restore <op0>, <op1>, %o[0-7]
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unsigned reg = AddMI->getOperand(0).getReg();
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if (reg < SP::I0 || reg > SP::I7)
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return false;
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// Erase RESTORE.
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RestoreMI->eraseFromParent();
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// Change ADD to RESTORE.
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AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
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? SP::RESTORErr
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: SP::RESTOREri));
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// Map the destination register.
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AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
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return true;
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}
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static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI,
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MachineBasicBlock::iterator OrMI,
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const TargetInstrInfo *TII)
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{
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// Before: or <op0>, <op1>, %i[0-7]
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// restore %g0, %g0, %i[0-7]
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// and <op0> or <op1> is zero,
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//
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// After : restore <op0>, <op1>, %o[0-7]
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unsigned reg = OrMI->getOperand(0).getReg();
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if (reg < SP::I0 || reg > SP::I7)
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return false;
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// check whether it is a copy.
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if (OrMI->getOpcode() == SP::ORrr
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&& OrMI->getOperand(1).getReg() != SP::G0
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&& OrMI->getOperand(2).getReg() != SP::G0)
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return false;
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if (OrMI->getOpcode() == SP::ORri
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&& OrMI->getOperand(1).getReg() != SP::G0
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&& (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
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return false;
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// Erase RESTORE.
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RestoreMI->eraseFromParent();
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// Change OR to RESTORE.
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OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
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? SP::RESTORErr
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: SP::RESTOREri));
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// Map the destination register.
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OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
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return true;
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}
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static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI,
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MachineBasicBlock::iterator SetHiMI,
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const TargetInstrInfo *TII)
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{
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// Before: sethi imm3, %i[0-7]
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// restore %g0, %g0, %g0
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//
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// After : restore %g0, (imm3<<10), %o[0-7]
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unsigned reg = SetHiMI->getOperand(0).getReg();
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if (reg < SP::I0 || reg > SP::I7)
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return false;
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if (!SetHiMI->getOperand(1).isImm())
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return false;
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int64_t imm = SetHiMI->getOperand(1).getImm();
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// Is it a 3 bit immediate?
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if (!isInt<3>(imm))
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return false;
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// Make it a 13 bit immediate.
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imm = (imm << 10) & 0x1FFF;
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assert(RestoreMI->getOpcode() == SP::RESTORErr);
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RestoreMI->setDesc(TII->get(SP::RESTOREri));
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RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
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RestoreMI->getOperand(1).setReg(SP::G0);
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RestoreMI->getOperand(2).ChangeToImmediate(imm);
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// Erase the original SETHI.
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SetHiMI->eraseFromParent();
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return true;
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}
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bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI)
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{
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// No previous instruction.
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if (MBBI == MBB.begin())
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return false;
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// assert that MBBI is a "restore %g0, %g0, %g0".
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assert(MBBI->getOpcode() == SP::RESTORErr
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&& MBBI->getOperand(0).getReg() == SP::G0
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&& MBBI->getOperand(1).getReg() == SP::G0
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&& MBBI->getOperand(2).getReg() == SP::G0);
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MachineBasicBlock::iterator PrevInst = std::prev(MBBI);
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// It cannot be combined with a bundled instruction.
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if (PrevInst->isBundledWithSucc())
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return false;
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const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo();
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switch (PrevInst->getOpcode()) {
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default: break;
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case SP::ADDrr:
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case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break;
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case SP::ORrr:
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case SP::ORri: return combineRestoreOR(MBBI, PrevInst, TII); break;
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case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break;
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}
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// It cannot combine with the previous instruction.
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return false;
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}
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