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llvm-6502/lib/Target/R600
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Matt Arsenault b1beec140e R600: Fix operand encoding error 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229609 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:10:42 +00:00
..
AsmParser
R600/SI: Add a stub GCNTargetMachine
2015-01-06 18:00:21 +00:00
InstPrinter
[cleanup] Re-sort all the #include lines in LLVM using
2015-01-14 11:23:27 +00:00
MCTargetDesc
Removing LLVM_DELETED_FUNCTION, as MSVC 2012 was the last reason for requiring the macro. NFC; LLVM edition.
2015-02-15 22:54:22 +00:00
TargetInfo
R600/SI: Add a stub GCNTargetMachine
2015-01-06 18:00:21 +00:00
AMDGPU.h
[PM] Remove a bunch of stale TTI creation method declarations. I nuked
2015-02-01 00:22:15 +00:00
AMDGPU.td
R600/SI: Add subtarget feature for if f32 fma is fast
2015-01-29 19:34:25 +00:00
AMDGPUAlwaysInlinePass.cpp
Reapply: R600: Make sure to inline all internal functions
2014-11-03 19:49:05 +00:00
AMDGPUAsmPrinter.cpp
Compute the ELF SectionKind from the flags.
2015-01-29 17:33:21 +00:00
AMDGPUAsmPrinter.h
std::unique_ptrify the MCStreamer argument to createAsmPrinter
2015-01-18 20:29:04 +00:00
AMDGPUCallingConv.td
…
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUInstrInfo.cpp
Make helper functions/classes/globals static. NFC.
2015-02-06 17:51:54 +00:00
AMDGPUInstrInfo.h
R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2
2015-02-03 17:37:57 +00:00
AMDGPUInstrInfo.td
R600/SI: Fix implicit vcc operand to v_div_fmas_*
2015-02-14 04:22:00 +00:00
AMDGPUInstructions.td
R600/SI: Extend private extload pattern to include zext loads
2015-02-17 16:36:00 +00:00
AMDGPUIntrinsicInfo.cpp
…
AMDGPUIntrinsicInfo.h
…
AMDGPUIntrinsics.td
…
AMDGPUISelDAGToDAG.cpp
R600/SI: Use complex operand folding for div_scale
2015-02-14 04:24:28 +00:00
AMDGPUISelLowering.cpp
R600/SI: Fix implicit vcc operand to v_div_fmas_*
2015-02-14 04:22:00 +00:00
AMDGPUISelLowering.h
Reuse a bunch of cached subtargets and remove getSubtarget calls
2015-01-30 23:24:40 +00:00
AMDGPUMachineFunction.cpp
R600: Canonicalize access to function attributes, NFC
2015-02-14 02:45:45 +00:00
AMDGPUMachineFunction.h
Reapply "R600: Add new intrinsic to read work dimensions"
2014-10-14 20:05:26 +00:00
AMDGPUMCInstLower.cpp
Reuse a bunch of cached subtargets and remove getSubtarget calls
2015-01-30 23:24:40 +00:00
AMDGPUMCInstLower.h
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
AMDGPUPromoteAlloca.cpp
R600: Don't promote allocas when one of the users is a ptrtoint instruction
2014-10-31 20:52:04 +00:00
AMDGPURegisterInfo.cpp
R600/SI: Enable inline assembly
2014-12-03 04:08:00 +00:00
AMDGPURegisterInfo.h
…
AMDGPURegisterInfo.td
…
AMDGPUSubtarget.cpp
Reuse a bunch of cached subtargets and remove getSubtarget calls
2015-01-30 23:24:40 +00:00
AMDGPUSubtarget.h
R600/SI: Disable subreg liveness
2015-02-11 18:24:53 +00:00
AMDGPUTargetMachine.cpp
[PM] Remove the old 'PassManager.h' header file at the top level of
2015-02-13 10:01:29 +00:00
AMDGPUTargetMachine.h
R600: Split AMDGPUPassConfig into R600PassConfig and GCNPassConfig
2015-02-11 17:11:51 +00:00
AMDGPUTargetTransformInfo.cpp
R600/SI: Fix bug in TTI loop unrolling preferences
2015-02-05 15:32:18 +00:00
AMDGPUTargetTransformInfo.h
[multiversion] Remove the function parameter from the unrolling
2015-02-01 14:31:23 +00:00
AMDILCFGStructurizer.cpp
…
AMDKernelCodeT.h
R600/SI: Emit amd_kernel_code_t header for AMDGPU environment
2014-12-02 22:00:07 +00:00
CaymanInstructions.td
R600/SI: Implement correct f64 fdiv
2015-02-14 04:30:08 +00:00
CIInstructions.td
Reuse a bunch of cached subtargets and remove getSubtarget calls
2015-01-30 23:24:40 +00:00
CMakeLists.txt
R600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 15:42:31 +00:00
EvergreenInstructions.td
R600/SI: Implement correct f64 fdiv
2015-02-14 04:30:08 +00:00
LLVMBuild.txt
R600/SI: Start implementing an assembler
2014-11-14 14:08:00 +00:00
Makefile
R600/SI: Start implementing an assembler
2014-11-14 14:08:00 +00:00
Processors.td
R600/SI: Add subtarget feature for if f32 fma is fast
2015-01-29 19:34:25 +00:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
Reuse a bunch of cached subtargets and remove getSubtarget calls
2015-01-30 23:24:40 +00:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
…
R600InstrFormats.td
R600/SI: Start implementing an assembler
2014-11-14 14:08:00 +00:00
R600InstrInfo.cpp
Remove unused argument to CreateTargetScheduleState and change
2014-10-09 01:59:35 +00:00
R600InstrInfo.h
Remove unused argument to CreateTargetScheduleState and change
2014-10-09 01:59:35 +00:00
R600Instructions.td
R600: Fix operand encoding error
2015-02-18 02:10:42 +00:00
R600Intrinsics.td
…
R600ISelLowering.cpp
Prefer SmallVector::append/insert over push_back loops.
2015-02-17 15:29:18 +00:00
R600ISelLowering.h
Reuse a bunch of cached subtargets and remove getSubtarget calls
2015-01-30 23:24:40 +00:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
[PM] Remove the old 'PassManager.h' header file at the top level of
2015-02-13 10:01:29 +00:00
R600MachineScheduler.h
…
R600OptimizeVectorRegisters.cpp
…
R600Packetizer.cpp
Reuse a bunch of cached subtargets and remove getSubtarget calls
2015-01-30 23:24:40 +00:00
R600RegisterInfo.cpp
…
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600TextureIntrinsicsReplacer.cpp
…
R700Instructions.td
Reuse a bunch of cached subtargets and remove getSubtarget calls
2015-01-30 23:24:40 +00:00
SIAnnotateControlFlow.cpp
R600/SI: Fix bug from insertion of llvm.SI.end.cf into loop headers
2015-02-05 15:32:15 +00:00
SIDefines.h
R600/SI: Also enable WQM for image opcodes which calculate LOD v3
2015-02-06 02:51:20 +00:00
SIFixSGPRCopies.cpp
R600/SI: Remove VReg_32 register class
2015-01-07 20:59:25 +00:00
SIFixSGPRLiveRanges.cpp
…
SIFoldOperands.cpp
R600/SI: Fix asam errors in SIFoldOperands
2015-02-17 20:11:54 +00:00
SIInsertWaits.cpp
R600/SI: Fix dependency between instruction writing M0 and S_SENDMSG on VI (v2)
2015-02-03 17:37:52 +00:00
SIInstrFormats.td
R600/SI: Rename encoding field to match docs for VOP3b
2015-02-14 03:54:29 +00:00
SIInstrInfo.cpp
R600/SI: Fix brace identation
2015-02-18 02:04:31 +00:00
SIInstrInfo.h
R600/SI: Allow f64 inline immediates in i64 operands
2015-02-13 19:05:03 +00:00
SIInstrInfo.td
R600/SI: Fix encoding error from glc bit on VI SMRD instructions
2015-02-18 02:10:40 +00:00
SIInstructions.td
R600/SI: Add missing offset operand to buffer bothen
2015-02-18 02:04:38 +00:00
SIIntrinsics.td
…
SIISelLowering.cpp
Prefer SmallVector::append/insert over push_back loops.
2015-02-17 15:29:18 +00:00
SIISelLowering.h
Reuse a bunch of cached subtargets and remove getSubtarget calls
2015-01-30 23:24:40 +00:00
SILoadStoreOptimizer.cpp
Reuse a bunch of cached subtargets and remove getSubtarget calls
2015-01-30 23:24:40 +00:00
SILowerControlFlow.cpp
R600/SI: Don't enable WQM for V_INTERP_* instructions v2
2015-02-06 02:51:25 +00:00
SILowerI1Copies.cpp
R600/SI: Remove VReg_32 register class
2015-01-07 20:59:25 +00:00
SIMachineFunctionInfo.cpp
R600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 15:42:31 +00:00
SIMachineFunctionInfo.h
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
2015-01-20 19:33:04 +00:00
SIPrepareScratchRegs.cpp
R600/SI: Fix simple-loop.ll test
2015-01-20 19:33:02 +00:00
SIRegisterInfo.cpp
R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2
2015-02-03 17:37:57 +00:00
SIRegisterInfo.h
R600/SI: Define a schedule model and enable the generic machine scheduler
2015-01-29 16:55:25 +00:00
SIRegisterInfo.td
R600/SI: Really fix size of VReg_1
2015-02-14 03:54:32 +00:00
SISchedule.td
R600/SI: Define a schedule model
2015-01-14 01:13:19 +00:00
SIShrinkInstructions.cpp
R600/SI: Allow f64 inline immediates in i64 operands
2015-02-13 19:05:03 +00:00
SITypeRewriter.cpp
R600: Canonicalize access to function attributes, NFC
2015-02-14 02:45:45 +00:00
VIInstrFormats.td
R600/SI: Fix VOP3b encoding on VI
2015-02-14 03:02:23 +00:00
VIInstructions.td
R600/SI: Add VI versions of MUBUF loads and stores
2015-01-27 17:24:58 +00:00