mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0b8c9a80f2
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
97 lines
3.2 KiB
C++
97 lines
3.2 KiB
C++
//===-- SparcTargetMachine.h - Define TargetMachine for Sparc ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Sparc specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARCTARGETMACHINE_H
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#define SPARCTARGETMACHINE_H
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#include "SparcFrameLowering.h"
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#include "SparcISelLowering.h"
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#include "SparcInstrInfo.h"
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#include "SparcSelectionDAGInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetTransformImpl.h"
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namespace llvm {
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class SparcTargetMachine : public LLVMTargetMachine {
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SparcSubtarget Subtarget;
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const DataLayout DL; // Calculates type size & alignment
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SparcInstrInfo InstrInfo;
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SparcTargetLowering TLInfo;
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SparcSelectionDAGInfo TSInfo;
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SparcFrameLowering FrameLowering;
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ScalarTargetTransformImpl STTI;
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VectorTargetTransformImpl VTTI;
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public:
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SparcTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool is64bit);
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virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
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virtual const TargetFrameLowering *getFrameLowering() const {
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return &FrameLowering;
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}
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virtual const SparcSubtarget *getSubtargetImpl() const{ return &Subtarget; }
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virtual const SparcRegisterInfo *getRegisterInfo() const {
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return &InstrInfo.getRegisterInfo();
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}
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virtual const SparcTargetLowering* getTargetLowering() const {
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return &TLInfo;
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}
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virtual const SparcSelectionDAGInfo* getSelectionDAGInfo() const {
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return &TSInfo;
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}
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virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
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return &STTI;
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}
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virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
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return &VTTI;
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}
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virtual const DataLayout *getDataLayout() const { return &DL; }
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// Pass Pipeline Configuration
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virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
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};
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/// SparcV8TargetMachine - Sparc 32-bit target machine
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///
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class SparcV8TargetMachine : public SparcTargetMachine {
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virtual void anchor();
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public:
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SparcV8TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// SparcV9TargetMachine - Sparc 64-bit target machine
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///
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class SparcV9TargetMachine : public SparcTargetMachine {
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virtual void anchor();
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public:
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SparcV9TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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